mlxbf_gige: compute MDIO period based on i1clk

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[ Upstream commit 3a1a274e93 ]

This patch adds logic to compute the MDIO period based on
the i1clk, and thereafter write the MDIO period into the YU
MDIO config register. The i1clk resource from the ACPI table
is used to provide addressing to YU bootrecord PLL registers.
The values in these registers are used to compute MDIO period.
If the i1clk resource is not present in the ACPI table, then
the current default hardcorded value of 430Mhz is used.
The i1clk clock value of 430MHz is only accurate for boards
with BF2 mid bin and main bin SoCs. The BF2 high bin SoCs
have i1clk = 500MHz, but can support a slower MDIO period.

Fixes: f92e1869d7 ("Add Mellanox BlueField Gigabit Ethernet driver")
Reviewed-by: Asmaa Mnebhi <asmaa@nvidia.com>
Signed-off-by: David Thompson <davthompson@nvidia.com>
Link: https://lore.kernel.org/r/20220826155916.12491-1-davthompson@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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David Thompson 2022-08-26 11:59:16 -04:00 • committed by Greg Kroah-Hartman

parent 4854a59b9a

commit 1579573b69

3 changed files with 110 additions and 18 deletions

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4

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h

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128

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c

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2

drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_regs.h

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