mtd: rawnand: sunxi: fix H6/H616 controller timings

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The NAND timing calculation assumes that command and address setup and
hold intervals T1-T4, T7 and T11 each take one controller clock. It also
uses the original A10 delay encodings for tWB, tADL, tWHR and tRHW.

The H6/H616 NDFC defines the setup and hold intervals as two internal
clock cycles and uses different delay encodings. Add the H616 timing
characteristics and select them through the controller capability data so
the clock solver and timing fields match the hardware.

Fixes: 88fd4e4dea ("mtd: rawnand: sunxi: Add support for H616 nand controller")
Cc: stable@vger.kernel.org
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

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James Hilliard 2026-08-07 09:39:01 -06:00 • committed by Miquel Raynal

parent 147f2a5743

commit 15a3cbce32

1 changed files with 36 additions and 13 deletions

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drivers/mtd/nand/raw/sunxi_nand.c

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