drm/amd/display: avoid dig reg access timeout on usb4 link training fail

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[Why]
When usb4 link training fails, the dpia sym clock will be disabled and SYMCLK
source should be changed back to phy clock. In enable_streams, it is
assumed that link training succeeded and will switch from refclk to
phy clock. But phy clk here might not be on. Dig reg access timeout
will occur.

[How]
When enable_stream is hit, check if link training failed for usb4.
If it did, fall back to the ref clock to avoid reg access timeout.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Zhongwei <Zhongwei.Zhang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Zhongwei 2026-01-13 15:51:42 +08:00 • committed by Alex Deucher

parent c37084e25f

commit 15b1d7b77e

1 changed files with 10 additions and 2 deletions

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drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

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