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can: flexcan: add correctable errors correction when HW supports ECC
commitcdce844865("can: flexcan: add vf610 support for FlexCAN") From above commit by Stefan Agner, the patch just disables non-correctable errors interrupt and freeze mode. It still can correct the correctable errors since ECC enabled by default after reset (MECR[ECCDIS]=0, enable memory error correct) if HW supports ECC. commit5e269324db("can: flexcan: disable completely the ECC mechanism") From above commit by Joakim Zhang, the patch disables ECC completely (assert MECR[ECCDIS]) according to the explanation of FLEXCAN_QUIRK_DISABLE_MECR that disable memory error detection. This cause correctable errors cannot be corrected even HW supports ECC. The error correction mechanism ensures that in this 13-bit word, errors in one bit can be corrected (correctable errors) and errors in two bits can be detected but not corrected (non-correctable errors). Errors in more than two bits may not be detected. If HW supports ECC, we can use this to correct the correctable errors detected from FlexCAN memory. Then disable non-correctable errors interrupt and freeze mode to avoid that put FlexCAN in freeze mode. This patch adds correctable errors correction when HW supports ECC, and modify explanation for FLEXCAN_QUIRK_DISABLE_MECR. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20200416093126.15242-1-qiangqing.zhang@nxp.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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