MIPS: Loongson64: Remove CPU_HAS_WB

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Q: Do we have really have write buffer
A: Yes, on newer Loongson processors there is a "store fill buffer"
   that will collect *cached* writes, on all Loongson processors
   AXI crossbar will buffer all writes.

Q: Then why do we want to remove CPU_HAS_WB?
A: Because CPU_HAS_WB introduces wbflush, which intends to flush
   all write reuqests to mmio device. We won't be affected by store
   fill buffer because it won't buffer uncached writes. And a regular
   memory barrier is sufficient to flush crossbar write buffer.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

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Jiaxun Yang 2023-02-21 13:16:57 +00:00 • committed by Thomas Bogendoerfer

parent 227003cb53

commit 162e134aed

2 changed files with 0 additions and 16 deletions

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arch/mips/Kconfig

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15

arch/mips/loongson64/setup.c

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