drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink

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If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.

v2:
* ACtually set the dpcd msa ignore bit (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com

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This commit is contained in:

Manasi Navare 2021-01-22 15:26:42 -08:00

parent f065123299

commit 1639406a31

2 changed files with 20 additions and 1 deletions

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19

drivers/gpu/drm/i915/display/intel_ddi.c

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2

drivers/gpu/drm/i915/display/intel_dp_link_training.c

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