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First round of updates for meson clocks targeted at v4.19
* Remove legacy register access (finish moving to syscon) * Clean up configuration flags * Add axg PCIe clocks * Add GEN CLK on gxbb, gxl and axg * Remove clk_audio_divider driver * Add axg audio clock controller -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAltDV88ACgkQ5vwPHDfy 2oWk1w//bKOHNvjBEqkA5kZcFd6hQ81KP0poG3QoZqd9Mkvj7sT1GOUVm8QS9oll neVXUT6JIavwOobwnD6f7WCNSHJ6buWTlnxJc37JJU81PBhCV2t2owhLkItSf/ni GDK/BhGf/vGCIAvjlfU2Bh2crxG7hXGVMeg8OFG99my9WryXPL1HaGJfO6ge1T26 N7Gx1bFAdf2wAK3B/EpCPNBYsnS+ohJz0Cq1S8BbJXOpMLjgAsR7UB25F+DCCjp2 pPSHq7gNKUVcgZKveiy2xRqj8F/j3eQyF9tr6K3mpx0obFzXXxFT8meMR54a6y61 swJ6E0PI9+u9kOOo7KOAEuLBIpamgIP19BJNLmXxb+ibAjKjp/mUc7i5qBoqvCOW 8Rab8Yc9/PP03VPY+Pm66OrryrsLciVX9vcSCA5TPXTzp5chyM9Yi9ZsP0QQEC2f NY7A55aL7WfHJsG28NxGEsbAf4F9ozvIFgg4FFPBq/kFlf/wZeWGtz3JPyhK84I6 yxsQbCFDqyFCNJvwPnMVKmGuui26E7w2Ctf8pdWt+/Amnd2kHekJRDi5dx/d5RK6 UhRrrckBBqV3C8UweQZZPPz7aBEA4SYnxwUc9w1jU9l2osbn0WAA/wuOuVEUVRAg 5675tDnmZwVpVmxnMH8aZH0ykaNPX7jk/XLHTdDHqk8NRDUKHRk= =w4lD -----END PGP SIGNATURE----- Merge tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson into clk-meson Pull first round of updates for meson clocks from Jerome Brunet: - Remove legacy register access (finish moving to syscon) - Clean up configuration flags - Add axg PCIe clocks - Add GEN CLK on gxbb, gxl and axg - Remove clk_audio_divider driver - Add axg audio clock controller * tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson: clk: meson: add gen_clk clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition clk: meson-axg: add clocks required by pcie driver clk: meson: remove unused clk-audio-divider driver clk: meson: stop rate propagation for audio clocks clk: meson: axg: add the audio clock controller driver clk: meson: add axg audio sclk divider driver clk: meson: add triple phase clock driver clk: meson: add clk-phase clock driver clk: meson: clean-up meson clock configuration clk: meson: remove obsolete register access clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings clk: meson: audio-divider is one based clk: add duty cycle support clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
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