drm/vc4: Increase the core clock based on HVS load

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Depending on a given HVS output (HVS to PixelValves) and input (planes
attached to a channel) load, the HVS needs for the core clock to be
raised above its boot time default.

Failing to do so will result in a vblank timeout and a stalled display
pipeline.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20211025152903.1088803-11-maxime@cerno.tech

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Maxime Ripard 2021-10-25 17:29:03 +02:00

parent b7551457c5

commit 16e101051f

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GPG key ID: E3EF0D6F671851C5

3 changed files with 118 additions and 9 deletions

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15

drivers/gpu/drm/vc4/vc4_crtc.c

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2

drivers/gpu/drm/vc4/vc4_drv.h

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110

drivers/gpu/drm/vc4/vc4_kms.c

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