clk: at91: fix div by zero in USB clock driver

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Test rate value before calculating the div value to avoid div by zero.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

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Boris BREZILLON 2014-09-02 09:50:18 +02:00 • committed by Mike Turquette

parent 13a6073d4c

commit 16eeaec779

1 changed files with 5 additions and 2 deletions

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drivers/clk/at91/clk-usb.c

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