From eaada4f56ab366f4c198291aa9d04b8a3348e291 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:25:24 +0100 Subject: [PATCH 01/47] arm64: dts: airoha: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/airoha/en7581-evb.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts index dae9968a4ff6..886e2e4b5f64 100644 --- a/arch/arm64/boot/dts/airoha/en7581-evb.dts +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts @@ -47,17 +47,17 @@ reg = <0x00600000 0x03200000>; }; - tclinux_slave@3800000 { + tclinux-slave@3800000 { label = "tclinux_alt"; reg = <0x03800000 0x03200000>; }; - rootfs_data@6a00000 { + rootfs-data@6a00000 { label = "rootfs_data"; reg = <0x06a00000 0x01400000>; }; - reserved_bmt@7e00000 { + reserved-bmt@7e00000 { label = "reserved_bmt"; reg = <0x07e00000 0x00200000>; read-only; From 0516c548883bbe58a48d604e81e33b390986cdb6 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 19 Nov 2025 18:51:22 +0100 Subject: [PATCH 02/47] arm64: dts: mediatek: mt7986: add dtbs with applied overlays for bpi-r3 Build devicetree binaries for testing overlays and providing users full dtb without using overlays. Suggested-by: Rob Herring Signed-off-by: Frank Wunderlich Acked-by: Rob Herring (Arm) Acked-by: AngeloGioacchino Del Regno Fixes: a58c36806741 ("arm64: dts: mediatek: mt7988a-bpi-r4pro: Add mmc overlays") Fixes: dec929e61a42 ("arm64: dts: mediatek: mt7988a-bpi-r4-pro: Add PCIe overlays") Fixes: 714a80ced07a ("arm64: dts: mediatek: mt7988a-bpi-r4: Add dt overlays for sd + emmc") Fixes: 312189ebb802 ("arm64: dts: mt7986: add overlay for SATA power socket on BPI-R3") Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c5fd6191a925..77d76730d61b 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -19,6 +19,27 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo +mt7986a-bananapi-bpi-r3-emmc-nand-dtbs := \ + mt7986a-bananapi-bpi-r3.dtb \ + mt7986a-bananapi-bpi-r3-emmc.dtbo \ + mt7986a-bananapi-bpi-r3-nand.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc-nand.dtb +mt7986a-bananapi-bpi-r3-emmc-nor-dtbs := \ + mt7986a-bananapi-bpi-r3.dtb \ + mt7986a-bananapi-bpi-r3-emmc.dtbo \ + mt7986a-bananapi-bpi-r3-nor.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc-nor.dtb +mt7986a-bananapi-bpi-r3-sd-nand-dtbs := \ + mt7986a-bananapi-bpi-r3.dtb \ + mt7986a-bananapi-bpi-r3-sd.dtbo \ + mt7986a-bananapi-bpi-r3-nand.dtbo \ + mt7986a-bananapi-bpi-r3-sata.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd-nand.dtb +mt7986a-bananapi-bpi-r3-sd-nor-dtbs := \ + mt7986a-bananapi-bpi-r3.dtb \ + mt7986a-bananapi-bpi-r3-sd.dtbo \ + mt7986a-bananapi-bpi-r3-nor.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd-nor.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb From d977b61d38030f50bae9f634049110af0a364d0d Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 19 Nov 2025 18:51:23 +0100 Subject: [PATCH 03/47] arm64: dts: mediatek: mt7988: add dtbs with applied overlays for bpi-r4 (pro) Build devicetree binaries for testing overlays and providing users full dtb without using overlays for Bananapi R4 (pro) variants. Signed-off-by: Frank Wunderlich Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 77d76730d61b..cac8f4c6d76f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -52,6 +52,38 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn18.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo +mt7988a-bananapi-bpi-r4-emmc-dtbs := \ + mt7988a-bananapi-bpi-r4.dtb \ + mt7988a-bananapi-bpi-r4-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtb +mt7988a-bananapi-bpi-r4-sd-dtbs := \ + mt7988a-bananapi-bpi-r4.dtb \ + mt7988a-bananapi-bpi-r4-sd.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtb +mt7988a-bananapi-bpi-r4-2g5-emmc-dtbs := \ + mt7988a-bananapi-bpi-r4-2g5.dtb \ + mt7988a-bananapi-bpi-r4-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-emmc.dtb +mt7988a-bananapi-bpi-r4-2g5-sd-dtbs := \ + mt7988a-bananapi-bpi-r4-2g5.dtb \ + mt7988a-bananapi-bpi-r4-sd.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-sd.dtb +mt7988a-bananapi-bpi-r4-pro-8x-emmc-dtbs := \ + mt7988a-bananapi-bpi-r4-pro-8x.dtb \ + mt7988a-bananapi-bpi-r4-pro-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-emmc.dtb +mt7988a-bananapi-bpi-r4-pro-8x-sd-dtbs := \ + mt7988a-bananapi-bpi-r4-pro-8x.dtb \ + mt7988a-bananapi-bpi-r4-pro-sd.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb +mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15-dtbs := \ + mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn15.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15.dtb +mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18-dtbs := \ + mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn18.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb From 34e7595912cfffdbca8c34d7c321d9937e0201ee Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 5 Dec 2025 22:59:38 +0100 Subject: [PATCH 04/47] arm64: dts: mediatek: Apply mt8395-radxa DT overlay at build time It's a requirement that DT overlays be applied at build time in order to validate them as overlays are not validated on their own. Add missing target for mt8395-radxa hd panel overlay. Fixes: 4c8ff61199a7 ("arm64: dts: mediatek: mt8395-radxa-nio-12l: Add Radxa 8 HD panel") Signed-off-by: Rob Herring (Arm) Signed-off-by: Frank Wunderlich Acked-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index cac8f4c6d76f..3f76d9ce9879 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -166,6 +166,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo +mt8395-radxa-nio-12l-8-hd-panel-dtbs := mt8395-radxa-nio-12l.dtb mt8395-radxa-nio-12l-8-hd-panel.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb # Device tree overlays support From be0b304eeb8c5f77e4f98f64e58729d879195f2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Otto=20Pfl=C3=BCger?= Date: Tue, 6 Jan 2026 11:11:12 +0100 Subject: [PATCH 05/47] arm64: dts: mediatek: mt8183: Add missing endpoint IDs to display graph MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The endpoint IDs in the display graph are expected to match the associated display path number, i.e. all endpoints connected to mmsys_ep_main must have reg = <0> and all endpoints connected to mmsys_ep_ext must have reg = <1>. Add the missing ID to all endpoints in the display graph, based on mt8365.dtsi as an existing example that does this correctly. Fixes: e72d63fa0563 ("arm64: dts: mediatek: mt8183: Migrate to display controller OF graph") Reported-by: Evans Jahja Closes: https://lore.kernel.org/linux-mediatek/CAAq5pW9o3itC0G16LnJO7KMAQ_XoqXUpB=cuJ_7e3-H11zKd5Q@mail.gmail.com/ Tested-by: Chen-Yu Tsai Signed-off-by: Otto Pflüger [Angelo: Fixed dtbs_check issues] Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 37 ++++++++++++++++++++---- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4e20a8f2eb25..95cc06799533 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1812,15 +1812,23 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - ovl_2l1_in: endpoint { + + ovl_2l1_in: endpoint@1 { + reg = <1>; remote-endpoint = <&mmsys_ep_ext>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - ovl_2l1_out: endpoint { + + ovl_2l1_out: endpoint@1 { + reg = <1>; remote-endpoint = <&rdma1_in>; }; }; @@ -1872,15 +1880,23 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - rdma1_in: endpoint { + + rdma1_in: endpoint@1 { + reg = <1>; remote-endpoint = <&ovl_2l1_out>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - rdma1_out: endpoint { + + rdma1_out: endpoint@1 { + reg = <1>; remote-endpoint = <&dpi_in>; }; }; @@ -2076,15 +2092,24 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - dpi_in: endpoint { + + dpi_in: endpoint@1 { + reg = <1>; remote-endpoint = <&rdma1_out>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - dpi_out: endpoint { }; + + dpi_out: endpoint@1 { + reg = <1>; + }; }; }; }; From 262cb81069c65373d4d6b773413552a65b478f7e Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:52 +0100 Subject: [PATCH 06/47] arm64: dts: mediatek: mt7981b: Add PCIe and USB support Add device tree nodes for PCIe controller and USB3 XHCI host controller on MT7981B SoC. Both controllers share the USB3 PHY which can be configured for either USB3 or PCIe operation. The USB3 XHCI controller supports USB 2.0 and USB 3.0 SuperSpeed operation. The PCIe controller is compatible with PCIe Gen2 specifications. Also add the topmisc syscon node required for USB/PCIe PHY multiplexing. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 416096b80770..d3f37413413e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include / { @@ -223,6 +224,55 @@ status = "disabled"; }; + xhci: usb@11200000 { + compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7981-pcie", + "mediatek,mt8192-pcie"; + reg = <0 0x11280000 0 0x4000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0 0x20000000 + 0x0 0x20000000 0 0x10000000>; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + device_type = "pci"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + interrupts = ; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, @@ -252,6 +302,36 @@ }; }; + topmisc: topmisc@11d10000 { + compatible = "mediatek,mt7981-topmisc", "syscon"; + reg = <0 0x11d10000 0 0x10000>; + #clock-cells = <1>; + }; + + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7981-tphy", + "mediatek,generic-tphy-v2"; + ranges = <0 0 0x11e10000 0x1700>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + }; + }; + efuse@11f20000 { compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; reg = <0 0x11f20000 0 0x1000>; From 8f350dbb2e4a7eaa5de97c6502d004caa26eba1a Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:53 +0100 Subject: [PATCH 07/47] arm64: dts: mediatek: mt7981b-openwrt-one: Enable PCIe and USB Enable the PCIe controller and USB3 XHCI host on the OpenWrt One board. The USB controller is configured for USB 2.0 only mode, as the shared USB3/PCIe PHY is dedicated to PCIe functionality on this board. Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 2e39e7287730..7382599cfea2 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -67,9 +67,40 @@ linux,default-trigger = "netdev"; }; }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; }; &pio { + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; + }; + }; + pwm_pins: pwm-pins { mux { function = "pwm"; @@ -163,3 +194,15 @@ &uart0 { status = "okay"; }; + +&usb_phy { + status = "okay"; +}; + +&xhci { + phys = <&u2port0 PHY_TYPE_USB2>; + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; From 9846a8c6031855ed9be45b4cc538c2b80965f816 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:54 +0100 Subject: [PATCH 08/47] arm64: dts: mediatek: mt7981b: Add Ethernet and WiFi offload support Add device tree nodes for the Ethernet subsystem on MT7981B SoC, including: - Ethernet MAC controller with dual GMAC support - Wireless Ethernet Dispatch (WED) - SGMII PHY controllers for high-speed Ethernet interfaces - Reserved memory regions for WiFi offload processor Signed-off-by: Sjoerd Simons [Angelo: Removed useless address/size cells from main eth node] Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 131 +++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index d3f37413413e..e277adcaf893 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -47,11 +48,36 @@ #size-cells = <2>; ranges; + wo_boot: wo-boot@15194000 { + reg = <0 0x15194000 0 0x1000>; + no-map; + }; + + wo_ilm0: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_dlm0: wo-dlm@151e8000 { + reg = <0 0x151e8000 0 0x2000>; + no-map; + }; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ secmon_reserved: secmon@43000000 { reg = <0 0x43000000 0 0x30000>; no-map; }; + + wo_emi0: wo-emi@47d80000 { + reg = <0 0x47d80000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@47dc0000 { + reg = <0 0x47dc0000 0 0x240000>; + no-map; + }; }; soc { @@ -107,6 +133,18 @@ #pwm-cells = <2>; }; + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x100>; @@ -345,15 +383,106 @@ thermal_calibration: thermal-calib@274 { reg = <0x274 0xc>; }; + + phy_calibration: phy-calib@8dc { + reg = <0x8dc 0x10>; + }; }; - clock-controller@15000000 { + ethsys: clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; + wed: wed@15010000 { + compatible = "mediatek,mt7981-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif0>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7981-eth"; + reg = <0 0x15100000 0 0x40000>; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, + <&topckgen CLK_TOP_CB_SGM_325M>; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&topckgen CLK_TOP_SGM_REG>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys0 CLK_SGM0_CK0_EN>, + <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <&sgmiisys1 CLK_SGM1_CK1_EN>, + <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu0", + "sgmii_ck", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; + sram = <ð_sram>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,infracfg = <&topmisc>; + mediatek,wed = <&wed>; + status = "disabled"; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-mode = "gmii"; + phy-is-integrated; + nvmem-cells = <&phy_calibration>; + nvmem-cell-names = "phy-cal-data"; + }; + }; + }; + + eth_sram: sram@15140000 { + compatible = "mmio-sram"; + reg = <0 0x15140000 0 0x40000>; + ranges = <0 0x15140000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = ; + }; + wifi@18000000 { compatible = "mediatek,mt7981-wmac"; reg = <0 0x18000000 0 0x1000000>, From ecc68d72b50d17241ec9d44dca11633589bd0049 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:55 +0100 Subject: [PATCH 09/47] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet Enable the Ethernet subsystem on OpenWrt One board with dual-MAC configuration: - GMAC0: Connected to external Airoha EN8811H 2.5GbE PHY via SGMII (2500base-x mode) for WAN connectivity with LED indicators - GMAC1: Connected to internal MT7981 1GbE PHY (GMII mode) for LAN Ethernet aliases are defined to provide consistent network interface naming (ethernet0 = LAN, ethernet1 = WAN). Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 7382599cfea2..2aea89900645 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -12,6 +12,8 @@ model = "OpenWrt One"; aliases { + ethernet0 = &gmac1; + ethernet1 = &gmac0; serial0 = &uart0; }; @@ -87,6 +89,58 @@ }; }; +ð { + status = "okay"; + + /* WAN interface */ + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + nvmem-cells = <&wan_factory_mac 0>; + nvmem-cell-names = "mac-address"; + phy-mode = "2500base-x"; + phy-handle = <&phy15>; + }; + + /* LAN interface */ + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + phy15: ethernet-phy@f { + compatible = "ethernet-phy-id03a2.a411"; + reg = <0xf>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_WAN; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_WAN; + color = ; + }; + }; + }; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -191,6 +245,10 @@ }; }; +&sgmiisys0 { + mediatek,pnswap; +}; + &uart0 { status = "okay"; }; From 46757ad083ce9a88ea157fe8b2b8f57d4db1801d Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:56 +0100 Subject: [PATCH 10/47] arm64: dts: mediatek: mt7981b: Disable wifi by default Disable the wifi block by default as it won't function properly without at least pin muxing. This doesn't enable wifi on any of the existing mt7981b devices as a required memory-region property is missing, causing the driver to fail probing anyway. Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index e277adcaf893..700f9c330bbb 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -497,6 +497,7 @@ clock-names = "mcu", "ap2conn"; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; + status = "disabled"; }; }; From c0379b6fa1645401c46a22845bb34d5498a3d1b5 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:57 +0100 Subject: [PATCH 11/47] arm64: dts: mediatek: mt7981b: Add wifi memory region Add required memory region for the builtin wifi block. Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 700f9c330bbb..324ae1395b3b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -69,6 +69,11 @@ no-map; }; + wmcpu_emi: wmcpu-reserved@47c80000 { + reg = <0 0x47c80000 0 0x100000>; + no-map; + }; + wo_emi0: wo-emi@47d80000 { reg = <0 0x47d80000 0 0x40000>; no-map; @@ -495,6 +500,7 @@ clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; clock-names = "mcu", "ap2conn"; + memory-region = <&wmcpu_emi>; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; status = "disabled"; From 6fd69ff487c6a4cb3f45e53684937975cb1b67c1 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:58 +0100 Subject: [PATCH 12/47] arm64: dts: mediatek: mt7981b-openwrt-one: Enable wifi Enable Dual-band WiFI 6 functionality on the Openwrt One Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 24 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 2aea89900645..3de368c73bc8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -180,6 +180,22 @@ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; }; }; + + wifi_dbdc_pins: wifi-dbdc-pins { + mux { + function = "eth"; + groups = "wf0_mode1"; + }; + + conf { + pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", + "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", + "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", + "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", + "WF_CBA_RESETB", "WF_DIG_RESETB"; + drive-strength = <4>; + }; + }; }; &pwm { @@ -257,6 +273,14 @@ status = "okay"; }; +&wifi { + nvmem-cells = <&wifi_factory_calibration>; + nvmem-cell-names = "eeprom"; + pinctrl-names = "dbdc"; + pinctrl-0 = <&wifi_dbdc_pins>; + status = "okay"; +}; + &xhci { phys = <&u2port0 PHY_TYPE_USB2>; vusb33-supply = <®_3p3v>; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 324ae1395b3b..4084f4dfa3e5 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -488,7 +488,7 @@ interrupts = ; }; - wifi@18000000 { + wifi: wifi@18000000 { compatible = "mediatek,mt7981-wmac"; reg = <0 0x18000000 0 0x1000000>, <0 0x10003000 0 0x1000>, From 6c90d33aedd355732062cc96d03fe4adb7609e8b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:03 +0100 Subject: [PATCH 13/47] arm64: dts: mediatek: mt8195: Add DPI1, HDMI, HDMI PHY/DDC nodes Add all of the nodes that are required to enable HDMI output, including ones describing the HDMI PHY, Controller and DDC, and the Digital Parallel Interface instance that is internally connected to the HDMI Controller. All of the added nodes are disabled by default as usage is board dependent. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 85 ++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c7adafaa8328..c72e34c57629 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -26,8 +26,10 @@ aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + dpi1 = &dpi1; gce0 = &gce0; gce1 = &gce1; + hdmi0 = &hdmi; ethdr0 = ðdr0; mutex0 = &mutex; mutex1 = &mutex1; @@ -1857,6 +1859,23 @@ #clock-cells = <1>; }; + hdmi_phy: hdmi-phy@11d5f000 { + compatible = "mediatek,mt8195-hdmi-phy"; + reg = <0 0x11d5f000 0 0x100>; + clocks = <&topckgen CLK_TOP_HDMI_XTAL>, + <&infracfg_ao CLK_INFRA_AO_HDMI_26M>, + <&apmixedsys CLK_APMIXED_HDMIPLL1>, + <&apmixedsys CLK_APMIXED_HDMIPLL2>; + clock-names = "pll_ref", "26m", "pll1", "pll2"; + clock-output-names = "hdmi_txpll"; + + #clock-cells = <0>; + #phy-cells = <0>; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "disabled"; + }; + i2c0: i2c@11e00000 { compatible = "mediatek,mt8195-i2c", "mediatek,mt8192-i2c"; @@ -3670,6 +3689,34 @@ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; }; + dpi1: dpi@1c112000 { + compatible = "mediatek,mt8195-dpi"; + reg = <0 0x1c112000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DPI1>, + <&vdosys1 CLK_VDO1_DPI1_MM>, + <&vdosys1 CLK_VDO1_DPI1_HDMI>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_DPI1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi1_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dpi1_out: endpoint { }; + }; + }; + }; + dp_intf1: dp-intf@1c113000 { compatible = "mediatek,mt8195-dp-intf"; reg = <0 0x1c113000 0 0x1000>; @@ -3730,6 +3777,44 @@ "gfx_fe1_async", "vdo_be_async"; }; + hdmi: hdmi-tx@1c300000 { + compatible = "mediatek,mt8195-hdmi-tx"; + #sound-dai-cells = <1>; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + assigned-clocks = <&topckgen CLK_TOP_HDCP>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + status = "disabled"; + + hdmitx_ddc: i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { }; + }; + }; + }; + edp_tx: edp-tx@1c500000 { compatible = "mediatek,mt8195-edp-tx"; reg = <0 0x1c500000 0 0x8000>; From 5875428ac6c7d687f9a51aef7c8665310f06be64 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:04 +0100 Subject: [PATCH 14/47] arm64: dts: mediatek: mt8188: Add DPI1, HDMI, HDMI PHY/DDC nodes Add all of the nodes that are required to enable HDMI output, including ones describing the HDMI PHY, Controller and DDC, and the Digital Parallel Interface instance that is internally connected to the HDMI Controller. All of the added nodes are disabled by default as usage is board dependent. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 82 ++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 90c388f1890f..e2a17359e407 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,6 +26,7 @@ aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + dpi1 = &dpi1; dsc0 = &dsc0; ethdr0 = ðdr0; gce0 = &gce0; @@ -2038,6 +2039,19 @@ }; }; + hdmi_phy: hdmi-phy@11d5f000 { + compatible = "mediatek,mt8188-hdmi-phy", "mediatek,mt8195-hdmi-phy"; + reg = <0 0x11d5f000 0 0x100>; + clocks = <&infracfg_ao CLK_INFRA_AO_HDMI_26M>; + clock-names = "pll_ref"; + clock-output-names = "hdmi_txpll"; + #clock-cells = <0>; + #phy-cells = <0>; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "disabled"; + }; + mipi_tx_config0: dsi-phy@11c80000 { compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; reg = <0 0x11c80000 0 0x1000>; @@ -3406,6 +3420,34 @@ mediatek,merge-fifo-en; }; + dpi1: dpi@1c112000 { + compatible = "mediatek,mt8188-dpi", "mediatek,mt8195-dpi"; + reg = <0 0x1c112000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DPI1>, + <&vdosys1 CLK_VDO1_DPI1_MM>, + <&vdosys1 CLK_VDO1_DPI1_HDMI>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_DPI1_MM_CK>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi1_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dpi1_out: endpoint { }; + }; + }; + }; + dp_intf1: dp-intf@1c113000 { compatible = "mediatek,mt8188-dp-intf"; reg = <0 0x1c113000 0 0x1000>; @@ -3530,6 +3572,46 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; }; + hdmi: hdmi@1c300000 { + compatible = "mediatek,mt8188-hdmi-tx"; + #sound-dai-cells = <1>; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + assigned-clocks = <&topckgen CLK_TOP_HDCP>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_HDMI_TX>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + status = "disabled"; + + hdmi_ddc: i2c { + compatible = "mediatek,mt8188-hdmi-ddc", + "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { }; + }; + }; + }; + + edp_tx: edp-tx@1c500000 { compatible = "mediatek,mt8188-edp-tx"; reg = <0 0x1c500000 0 0x8000>; From ae9198b7a5d64e01632cd450d4408f162f88c3be Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:05 +0100 Subject: [PATCH 15/47] arm64: dts: mediatek: mt8390-genio-common: Enable HDMI output Add a node for the HDMI-A connector found on this board, then configure the display pipeline and enable the required DPI1 interface, HDMI controller, its integrated DDC and the HDMI PHY to enable support for the HDMI output provided by these EVKs. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8390-genio-common.dtsi | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index a2cdecd2b903..5fa1f5fbad18 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -55,6 +55,20 @@ wakeup-delay-ms = <30>; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmi_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -328,6 +342,18 @@ remote-endpoint = <&dsi0_in>; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + &gamma0_out { remote-endpoint = <&postmask0_in>; }; @@ -337,6 +363,55 @@ status = "okay"; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -475,6 +550,35 @@ status = "okay"; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6359_vproc2_buck_reg>; }; @@ -727,6 +831,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = ; + bias-pull-down; + }; + + pins-cec { + pinmux = ; + bias-disable; + }; + + pins-ddc { + pinmux = , + ; + drive-strength = <10>; + }; + }; + i2c0_pins: i2c0-pins { pins { pinmux = , @@ -1286,6 +1415,18 @@ }; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { status = "okay"; }; From 0ad0f933fc0dad5a51996533d3cdb11a24c83e00 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:06 +0100 Subject: [PATCH 16/47] arm64: dts: mediatek: mt8390-genio-common: Add HDMI sound output support Add in the sound node a new dai-link for ETDM3_OUT_BE to add the sound output support through the HDMI connector. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index 5fa1f5fbad18..2062506f6cc5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -1344,6 +1344,15 @@ sound-dai = <&dmic_codec>; }; }; + + dai-link-2 { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; + }; &spi2 { From 19a385bd460e97b216c82603c01081f7b5c9e4ef Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:07 +0100 Subject: [PATCH 17/47] arm64: dts: mediatek: mt8395-radxa-nio-12l: Enable HDMI output Add a definition for the on-board HDMI connector, enable and add the relevant configuration for the HDMI PHY and controller, and define the pins used by those. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8395-radxa-nio-12l.dts | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index d32f973f5e05..b0e18876bd5d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -37,6 +37,20 @@ stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmitx_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -245,6 +259,18 @@ }; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>; @@ -265,11 +291,61 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &gpu { mali-supply = <&mt6315_7_vbuck1>; status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + + status = "okay"; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-0 = <&i2c2_pins>; @@ -448,6 +524,35 @@ }; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; @@ -647,6 +752,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = ; + bias-pull-down; + }; + + pins-ddc { + pinmux = , + ; + drive-strength = <10>; + }; + + pins-cec { + pinmux = ; + bias-disable; + }; + }; + i2c2_pins: i2c2-pins { pins-bus { pinmux = , @@ -1058,6 +1188,18 @@ status = "okay"; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { vbus-supply = <&otg_vbus_regulator>; status = "okay"; From 0ddfd2f29ae229fb67b710677e7d7004e685d733 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:08 +0100 Subject: [PATCH 18/47] arm64: dts: mediatek: mt8395-radxa-nio-12l: Add HDMI sound output support Add in the sound node a new dai-link for ETDM3_OUT_BE to add the sound output support through the HDMI TX connector. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index b0e18876bd5d..1cd4b84e9861 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -1072,6 +1072,14 @@ sound-dai = <&pmic 0>; }; }; + + hdmi-dai-link { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; }; &spi1 { From e1480453aed83e2b0d2e52a0e439c56bd4c3a4c4 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:09 +0100 Subject: [PATCH 19/47] arm64: dts: mediatek: mt8395-genio-common: Enable HDMI output Add a definition for the on-board HDMI connector, enable and add the relevant configuration for the HDMI PHY and controller, and define the pins used by those. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8395-genio-common.dtsi | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 2b7167804e71..345fc5ac9e03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -26,6 +26,20 @@ stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmitx_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -247,6 +261,18 @@ wakeup-delay-ms = <200>; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + &dsi0 { #address-cells = <1>; #size-cells = <0>; @@ -313,6 +339,35 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &gamma0_out { remote-endpoint = <&dither0_in>; }; @@ -329,6 +384,27 @@ status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-0 = <&i2c1_pins>; @@ -533,6 +609,35 @@ }; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; @@ -762,6 +867,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = ; + bias-pull-down; + }; + + pins-ddc { + pinmux = , + ; + drive-strength = <10>; + }; + + pins-cec { + pinmux = ; + bias-disable; + }; + }; + i2c0_pins: i2c0-pins { pins { pinmux = , @@ -1212,6 +1342,18 @@ }; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { status = "okay"; }; From 7fe8a313e4646ae4c5cb6a6e46b78bf5c9166066 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:10 +0100 Subject: [PATCH 20/47] arm64: dts: mediatek: mt8395-genio-common: Add HDMI sound output support Add in the sound node a new dai-link for ETDM3_OUT_BE to add the sound output support through the HDMI TX connector. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 345fc5ac9e03..d849af4d3613 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -1189,6 +1189,14 @@ sound-dai = <&pmic 0>; }; }; + + hdmi-dai-link { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; }; &spi1 { From a7a53f7482f96f88d6ab2064828f6f6bdb93c43e Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:37 +0100 Subject: [PATCH 21/47] dt-bindings: vendor-prefixes: Add Ezurio LLC Ezurio is the new name of Laird Connectivity after it acquired Boundary Devices. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..26e6935e5115 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -555,6 +555,8 @@ patternProperties: description: Exegin Technologies Limited "^ezchip,.*": description: EZchip Semiconductor + "^ezurio,.*": + description: Ezurio LLC "^facebook,.*": description: Facebook "^fairchild,.*": From 07a4700f95745671e8f257d56db6aaf244350111 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:38 +0100 Subject: [PATCH 22/47] dt-bindings: arm: mediatek: Add Ezurio Tungsten entries Add device tree bindings support for the Ezurio Tungsten 510 (MT8370) SMARC [1] / Ezurio Tungsten 700 (MT8390) SMARC [2] + Universal SMARC carrier board [3]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/product/tungsten700-smarc [3] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 718d732174b9..382d0eb4d0af 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -438,12 +438,14 @@ properties: - const: mediatek,mt8365 - items: - enum: + - ezurio,mt8370-tungsten-smarc - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 - items: - enum: + - ezurio,mt8390-tungsten-smarc - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 From 18e1d95faeaca2e1b3887d2c44fe44b8bb2f123c Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:39 +0100 Subject: [PATCH 23/47] arm64: dts: mediatek: mt8188: switch mmc nodes to interrupts-extended No functional change but will allow other dts including this one to override the interrupts, for eint support for instance, without having to delete the 'interrupts' property. Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index e2a17359e407..75133794cec3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1801,7 +1801,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11230000 0 0x10000>, <0 0x11f50000 0 0x1000>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC50_0>, <&infracfg_ao CLK_INFRA_AO_MSDC0>, <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, @@ -1814,7 +1814,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11240000 0 0x1000>, <0 0x11eb0000 0 0x1000>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC30_1>, <&infracfg_ao CLK_INFRA_AO_MSDC1>, <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; @@ -1828,7 +1828,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11250000 0 0x1000>, <0 0x11e60000 0 0x1000>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC30_2>, <&infracfg_ao CLK_INFRA_AO_MSDC2>, <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; From 9fda4a8a479f030a2a267b1823ffe0687aea8fd4 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:40 +0100 Subject: [PATCH 24/47] arm64: dts: mediatek: add device tree for Tungsten 510 board Add device tree to support Ezurio Tungsten 510 (MT8370) SMARC SOM [1] + Universal SMARC carrier board [2]. It includes support for the MIPI-DSI BD070LIC3 display which uses the Tianma TM070JDHG30 panel + TI SN65DSI84 MIPI-DSI to LVDS bridge [3]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier [3] https://www.ezurio.com/product/bd070lic3-7-touchscreen-display Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8370-tungsten-smarc.dts | 14 + .../dts/mediatek/mt8390-tungsten-smarc.dtsi | 1489 +++++++++++++++++ 3 files changed, 1504 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3f76d9ce9879..9e26d828d796 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts b/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts new file mode 100644 index 000000000000..4c3a7c4579c8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ +/dts-v1/; +#include "mt8370.dtsi" +#include "mt8390-tungsten-smarc.dtsi" + +/ { + model = "Ezurio Tungsten510 SMARC (MT8370)"; + compatible = "ezurio,mt8370-tungsten-smarc", "mediatek,mt8370", + "mediatek,mt8188"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi new file mode 100644 index 000000000000..40b381d4cc35 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi @@ -0,0 +1,1489 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ + +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + aliases { + dsi0 = &disp_dsi0; + ethernet0 = ð + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc2; + rtc0 = &rv3028; + rtc1 = &mt6359rtc; + serial0 = &uart0; + }; + + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <768>; + num-interpolated-steps = <1023>; + enable-gpios = <&pio 30 GPIO_ACTIVE_HIGH>; + pwms = <&disp_pwm0 0 30000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x1 0x00000000>; + }; + + panel-dsi0 { + compatible = "tianma,tm070jdhg30"; + backlight = <&backlight_lcd0>; + power-supply = <®_5v>; + + port { + dsi0_panel_in: endpoint { + remote-endpoint = <&sn65dsi84_bridge_out>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + regulator-efuse { + compatible = "regulator-output"; + vout-supply = <&mt6359_vefuse_ldo_reg>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "reg_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "reg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sdcard_en_3v3: regulator-sdcard-en { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "sdcard_en_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 111 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p0_vbus: regulator-usb-p0-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus_p0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator-usb-p1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_hub_pins>; + regulator-name = "vbus_p1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 147 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator-usb-p2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_eth_pins>; + regulator-name = "vbus_p2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pins>; + post-power-on-delay-ms = <200>; + reset-gpios = <&pio 89 GPIO_ACTIVE_LOW>; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&disp_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + +&disp_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi84_bridge_in>; + }; + }; + }; +}; + +&dither0_in { + remote-endpoint = <&postmask0_out>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio = <&pio 27 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 11000 1000>; + status = "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x7>; + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gamma0_out { + remote-endpoint = <&postmask0_in>; +}; + +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + i2c-mux@73 { + compatible = "nxp,pca9546"; + reg = <0x73>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_mux_pins>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_mux_gp_0: i2c@0 { + reg = <0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_1: i2c@1 { + reg = <1>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_2: i2c@2 { + reg = <2>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_3: i2c@3 { + reg = <3>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; + + i2c-mux@73 { + compatible = "nxp,pca9546"; + reg = <0x73>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_mux_smarc_lcd_pins>; + reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_mux_lcd_0: i2c@0 { + reg = <0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_1: i2c@1 { + reg = <1>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_2: i2c@2 { + reg = <2>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_3: i2c@3 { + reg = <3>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c_mux_gp_0 { + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + interrupts-extended = <&pio 42 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rv3028_pins>; + #clock-cells = <0>; + wakeup-source; + }; +}; + +&i2c_mux_gp_1 { + usb-typec@60 { + compatible = "ti,hd3ss3220"; + reg = <0x60>; + interrupts-extended = <&pio 45 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hd3ss3220_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb_role_switch>; + }; + }; + }; + }; +}; + +&i2c_mux_gp_2 { + codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&topckgen CLK_TOP_I2SO1>; + AVDD-supply = <®_1v8>; + CPVDD-supply = <®_1v8>; + DBVDD-supply = <®_3v3>; + DCVDD-supply = <®_1v8>; + MICVDD-supply = <®_3v3>; + PLLVDD-supply = <®_1v8>; + SPKVDD1-supply = <®_5v>; + SPKVDD2-supply = <®_5v>; + gpio-cfg = < + 0x0000 /* n/c */ + 0x0000 /* gpio2: */ + 0x0000 /* gpio3: */ + 0x0000 /* n/c */ + 0x8081 /* gpio5:HP detect */ + 0x8095 /* gpio6:Mic detect */ + >; + }; +}; + +&i2c_mux_lcd_2 { + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_sn65dsi84_pins>; + enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi84_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + sn65dsi84_bridge_out: endpoint { + remote-endpoint = <&dsi0_panel_in>; + }; + }; + }; + }; + + touchscren@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_dsi0_goodix_pins>; + interrupts-extended = <&pio 146 IRQ_TYPE_LEVEL_HIGH>; + irq-gpios = <&pio 146 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x1481b>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + non-removable; + no-sd; + no-sdio; + supports-cqe; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <200000000>; + sd-uhs-sdr104; + sd-uhs-sdr50; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; + vmmc-supply = <&sdcard_en_3v3>; + status = "okay"; +}; + +&mmc2 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <200000000>; + no-mmc; + non-removable; + no-sd; + sd-uhs-sdr104; + wakeup-source; + pinctrl-names = "default", "state_uhs", "state_eint"; + pinctrl-0 = <&mmc2_default_pins>; + pinctrl-1 = <&mmc2_uhs_pins>; + pinctrl-2 = <&mmc2_eint_pins>; + interrupt-names = "msdc", "sdio_wakeup"; + interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 172 IRQ_TYPE_LEVEL_LOW>; + vmmc-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vqmmc-supply = <&mt6359_vcn18_ldo_reg>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +&mipi_tx_config0 { + status = "okay"; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; + mediatek,mic-type-1 = <3>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name = "vcn18_pmu"; + regulator-always-on; + regulator-boot-on; +}; + +&mt6359_vcn33_1_bt_ldo_reg { + regulator-name = "vcn33_1_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name = "vcn33_2_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name = "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vemc_1_ldo_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name = "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vmodem_buck_reg { + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name = "vpa_pmu"; + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name = "vgpu"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <225000>; +}; + +&mt6359_vs2_buck_reg { + regulator-min-microvolt = <1600000>; + regulator-boot-on; +}; + +&mt6359_vpu_buck_reg { + regulator-name = "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name = "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread = <225000>; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name = "vsim1_pmu"; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name = "vufs18_pmu"; + regulator-always-on; +}; + +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default_pins>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + + keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = ; + wakeup-source; + }; + }; +}; + +&postmask0_in { + remote-endpoint = <&gamma0_out>; +}; + +&postmask0_out { + remote-endpoint = <&dither0_in>; +}; + +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-name = "vbuck1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck3: vbuck3 { + regulator-name = "vbuck3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck4: vbuck4 { + regulator-name = "vbuck4"; + regulator-min-microvolt = <1193750>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1193750>; + }; + }; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ssusb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + usb-role-switch; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usbotg_pins>; + pinctrl-names = "default"; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + + port@1 { + reg = <1>; + usb_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&u2port0 { + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&xhci0 { + vbus-supply = <&usb_p0_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb1 { + dr_mode = "host"; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&u2port1 { + status = "okay"; +}; + +&u3port1 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&xhci1 { + vbus-supply = <&usb_p1_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + dr_mode = "host"; + maximum-speed = "high-speed"; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&u2port2 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&xhci2 { + vbus-supply = <&usb_p2_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet@1 { + compatible = "usb424,7850"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <1>; + microchip,led-modes = < + LAN78XX_LINK_1000_ACTIVITY + LAN78XX_LINK_10_ACTIVITY + LAN78XX_LINK_10_100_ACTIVITY + LAN78XX_LINK_ACTIVITY + >; + }; + }; + }; +}; + +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; +}; + +&pio { + audio_pins: audio-pins { + pins-aud-pmic { + pinmux = ; + }; + + pins-pcm-wifi { + pinmux = ; + }; + + pins-i2s { + pinmux = ; + }; + }; + + disp_pwm0_pins: disp-pwm0-pins { + pins { + pinmux = ; + bias-pull-down; + }; + }; + + dsi0_sn65dsi84_pins: dsi0-sn65dsi84-pins { + pins-irq { + pinmux = ; + bias-pull-down; + input-enable; + }; + + pins-enable { + pinmux = ; + bias-pull-down; + }; + }; + + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + pins-cc { + pinmux = , + , + ; + drive-strength = <8>; + }; + pins-rxd { + pinmux = , + , + , + , + ; + drive-strength = <8>; + bias-pull-up = ; + }; + pins-mdio { + pinmux = , + ; + drive-strength = <8>; + input-enable; + }; + pins-power { + pinmux = ; /* GP_EQOS_RESET */ + output-high; + }; + pins-intr { + pinmux = ; /* GPIRQ_EQOS_PHY */ + bias-pull-up = ; + input-enable; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + pins-cc { + pinmux = , + , + , + ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + + gpio_keys_pins: gpio-keys-pins { + pins-keys { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + hd3ss3220_pins: hd3ss3320-pins { + pins-irq { + pinmux = ; + bias-pull-up = ; + input-enable; + }; + }; + + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = ; + bias-pull-down; + }; + + pins-cec { + pinmux = ; + bias-disable; + }; + + pins-ddc { + pinmux = , + ; + drive-strength = <10>; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c0_mux_pins: i2c0-mux-pins { + pins-reset { + pinmux = ; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c_mux_smarc_lcd_pins: i2c-mux-smarc-lcd-pins { + pins-reset { + pinmux = ; + bias-pull-down; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-pwr { + pinmux = ; + bias-pull-down; + }; + + pins-pullup { + pinmux = ; + bias-pull-up; + }; + + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux = ; + drive-strength = <4>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <4>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux = ; + input-enable; + bias-pull-up = ; + }; + }; + + rv3028_pins: rv3028-pins { + pins-irq { + pinmux = ; + bias-pull-up = ; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + pcie_default_pins: pcie-default-pins { + pins { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + ts_dsi0_goodix_pins: ts-dsi0-goodix-pins { + pins-irq { + pinmux = ; + bias-pull-up = ; + input-enable; + }; + + pins-reset { + pinmux = ; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + usbotg_pins: usbotg-pins { + pins-iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux = ; + input-enable; + }; + + pins-vbus { + pinmux = ; + output-high; + }; + }; + + usb1_hub_pins: usb1-hub-pins { + pins { + pinmux = ; + output-low; + }; + }; + + usb1_pins: usb1-pins { + pins { + pinmux = ; + input-enable; + }; + }; + + usb2_eth_pins: usb2-eth-pins { + pins { + pinmux = ; + output-low; + }; + }; + + wifi_pwrseq_pins: wifi-pwrseq-pins { + pins { + pinmux = ; + output-low; + }; + }; + + watchdog_pins: watchdog-pins { + pins { + pinmux = ; + bias-pull-up; + }; + }; +}; From fe96ff075f960abb9dd1c99c4c4e7f79c4e10172 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:41 +0100 Subject: [PATCH 25/47] arm64: dts: mediatek: add device tree for Tungsten 700 board Add device tree to support Ezurio Tungsten 700 (MT8390) SMARC SOM [1] + Universal SMARC carrier board [2]. It includes support for the MIPI-DSI BD070LIC3 display which uses the Tianma TM070JDHG30 panel + TI SN65DSI84 MIPI-DSI to LVDS bridge [3]. [1] https://www.ezurio.com/product/tungsten700-smarc [2] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier [3] https://www.ezurio.com/product/bd070lic3-7-touchscreen-display Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8390-tungsten-smarc.dts | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 9e26d828d796..387faa9c2a09 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -164,6 +164,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts new file mode 100644 index 000000000000..7580f9e2f20d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ +/dts-v1/; +#include "mt8188.dtsi" +#include "mt8390-tungsten-smarc.dtsi" + +/ { + model = "Ezurio Tungsten700 SMARC (MT8390)"; + compatible = "ezurio,mt8390-tungsten-smarc", "mediatek,mt8390", + "mediatek,mt8188"; +}; + +&cpu4 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu5 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; From c3f6d533b76e27a6dd4264b0240f7742a4d79323 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 12 Jan 2026 16:55:42 +0800 Subject: [PATCH 26/47] arm64: dts: mediatek: mt8188-geralt: drop firmware-name from first SCP core Arnd pointed out that having firmware-name in the device tree is wrong. Drop it. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index 7fedbacdac44..8e423504ec05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -1166,7 +1166,6 @@ &scp_c0 { pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; - firmware-name = "mediatek/mt8188/scp.img"; memory-region = <&scp_mem_reserved>; status = "okay"; }; From c68a509320a635f5bfa6c43d0c91c964a8fa678f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:37 +0100 Subject: [PATCH 27/47] arm64: dts: mediatek: mt8173: Fix pinctrl node names and cleanup Fix the pinctrl node names to adhere to the bindings, as the main pin node is supposed to be named like "uart0-pins" and the pinmux node named like "pins-bus". While at it, also cleanup all of the MTK_DRIVE_(x)mA by changing that to just the (x) number. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8173-elm-hana.dtsi | 34 ++--- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 138 +++++++++--------- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 60 ++++---- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 28 ++-- 4 files changed, 128 insertions(+), 132 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi index dfc5c2f0ddef..1004eb8ea52c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -5,6 +5,14 @@ #include "mt8173-elm.dtsi" +&hdmi_mux_pins { + pins-mux { + pinmux = ; + bias-pull-up; + output-high; + }; +}; + &i2c0 { clock-frequency = <200000>; }; @@ -67,26 +75,16 @@ }; }; -&mmc1 { - wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; +&mmc1_pins_default { + pins-wp { + pinmux = ; + input-enable; + bias-pull-up; + }; }; -&pio { - hdmi_mux_pins: hdmi_mux_pins { - pins2 { - pinmux = ; - bias-pull-up; - output-high; - }; - }; - - mmc1_pins_default: mmc1default { - pins_wp { - pinmux = ; - input-enable; - bias-pull-up; - }; - }; +&mmc1 { + wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; }; &touchscreen { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 0d995b342d46..9ec930058b92 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -601,8 +601,8 @@ "SOC_I2C4_1V8_SDA_400K", "SOC_I2C4_1V8_SCL_400K"; - aud_i2s2: aud_i2s2 { - pins1 { + aud_i2s2: aud-i2s2-pins { + pins-bus { pinmux = , , , @@ -614,55 +614,55 @@ }; }; - bl_fixed_pins: bl_fixed_pins { - pins1 { + bl_fixed_pins: backlight-pins { + pins-blon { pinmux = ; output-low; }; }; - bt_wake_pins: bt_wake_pins { - pins1 { + bt_wake_pins: bt-pins { + pins-wake { pinmux = ; bias-pull-up; }; }; - disp_pwm0_pins: disp_pwm0_pins { + disp_pwm0_pins: disp-pwm0-pins { pins1 { pinmux = ; output-low; }; }; - gpio_keys_pins: gpio_keys_pins { - volume_pins { + gpio_keys_pins: gpio-keys-pins { + pins-volumeupdn { pinmux = , ; bias-pull-up; }; - tablet_mode_pins { + pins-tabletmode { pinmux = ; bias-pull-up; }; }; - hdmi_mux_pins: hdmi_mux_pins { - pins1 { + hdmi_mux_pins: hdmi-pins { + pins-mux { pinmux = ; }; }; - i2c1_pins_a: i2c1 { - da9211_pins { + i2c1_pins_a: i2c1-pins { + pins-da9211 { pinmux = ; bias-pull-up; }; }; - mmc0_pins_default: mmc0default { - pins_cmd_dat { + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { pinmux = , , , @@ -675,68 +675,68 @@ bias-pull-up; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; - mmc1_pins_default: mmc1default { - pins_cmd_dat { + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { pinmux = , , , , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; - drive-strength = ; + drive-strength = <4>; }; - pins_insert { + pins-insert { pinmux = ; bias-pull-up; }; }; - mmc3_pins_default: mmc3default { - pins_dat { + mmc3_pins_default: mmc3-default-pins { + pins-dat { pinmux = , , , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; - pins_cmd { + pins-cmd { pinmux = ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; - drive-strength = ; + drive-strength = <8>; }; }; - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { pinmux = , , , @@ -747,109 +747,109 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; - pins_ds { + pins-ds { pinmux = ; drive-strength = ; bias-pull-down = ; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { + mmc1_pins_uhs: mmc1-pins { + pins-cmd-dat { pinmux = , , , , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; }; - mmc3_pins_uhs: mmc3 { - pins_dat { + mmc3_pins_uhs: mmc3-pins { + pins-dat { pinmux = , , , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; - pins_cmd { + pins-cmd { pinmux = ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; }; - nor_gpio1_pins: nor { + nor_gpio1_pins: nor-pins { pins1 { pinmux = , , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up; }; pins2 { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-up; }; - pins_clk { + pins-clk { pinmux = ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up; }; }; - panel_backlight_en_pins: panel_backlight_en_pins { + panel_backlight_en_pins: panel-backlight-en-pins { pins1 { pinmux = ; }; }; - panel_fixed_pins: panel_fixed_pins { + panel_fixed_pins: panel-fixed-pins { pins1 { pinmux = ; }; }; - ps8640_pins: ps8640_pins { + ps8640_pins: ps8640-pins { pins1 { pinmux = , , @@ -857,33 +857,33 @@ }; }; - ps8640_fixed_pins: ps8640_fixed_pins { + ps8640_fixed_pins: ps8640-fixed-pins { pins1 { pinmux = ; }; }; - rt5650_irq: rt5650_irq { - pins1 { + rt5650_irq: rt5650-pins { + pins-intn { pinmux = ; bias-pull-down; }; }; - sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { + sdio_fixed_3v3_pins: sdio-vreg-3v3-pins { pins1 { pinmux = ; output-low; }; }; - spi_pins_a: spi1 { + spi_pins_a: spi1-pins { pins1 { pinmux = ; bias-pull-up; }; - pins_spi { + pins-spi { pinmux = , , , @@ -892,15 +892,15 @@ }; }; - trackpad_irq: trackpad_irq { - pins1 { + trackpad_irq: trackpad-pins { + pins-intn { pinmux = ; input-enable; bias-pull-up; }; }; - usb_pins: usb { + usb_pins: usb-pins { pins1 { pinmux = ; output-high; @@ -908,8 +908,8 @@ }; }; - wifi_wake_pins: wifi_wake_pins { - pins1 { + wifi_wake_pins: wifi-pins { + pins-wake { pinmux = ; bias-pull-up; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 9fffed0ef4bf..51118a4149d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -172,15 +172,15 @@ }; &pio { - disp_pwm0_pins: disp_pwm0_pins { + disp_pwm0_pins: disp-pwm0-pins { pins1 { pinmux = ; output-low; }; }; - mmc0_pins_default: mmc0default { - pins_cmd_dat { + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { pinmux = , , , @@ -194,19 +194,19 @@ bias-pull-up; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; - mmc1_pins_default: mmc1default { - pins_cmd_dat { + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { pinmux = , , , @@ -217,20 +217,20 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; drive-strength = <4>; }; - pins_insert { + pins-insert { pinmux = ; bias-pull-up; }; }; - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { pinmux = , , , @@ -245,20 +245,29 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; drive-strength = <2>; bias-pull-down = ; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { + spi_pins_a: spi0-pins { + pins-bus { + pinmux = , + , + , + ; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-cmd-dat { pinmux = , , , @@ -269,22 +278,22 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; drive-strength = <4>; bias-pull-down = ; }; }; - usb_id_pins_float: usb_iddig_pull_up { - pins_iddig { + usb_id_pins_float: usb-iddig-pu-pins { + pins-iddig-pu { pinmux = ; bias-pull-up; }; }; - usb_id_pins_ground: usb_iddig_pull_down { - pins_iddig { + usb_id_pins_ground: usb-iddig-pd-pins { + pins-iddig-pd { pinmux = ; bias-pull-down; }; @@ -473,17 +482,6 @@ }; }; -&pio { - spi_pins_a: spi0 { - pins_spi { - pinmux = , - , - , - ; - }; - }; -}; - &spi { pinctrl-names = "default"; pinctrl-0 = <&spi_pins_a>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 122a57c3780b..78c2ccd5be13 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -391,58 +391,58 @@ , ; - hdmi_pin: xxx { + hdmi_pin: hdmi-hotplug-pins { /*hdmi htplg pin*/ - pins1 { + pins-htplg { pinmux = ; input-enable; bias-pull-down; }; }; - i2c0_pins_a: i2c0 { - pins1 { + i2c0_pins_a: i2c0-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c1_pins_a: i2c1 { - pins1 { + i2c1_pins_a: i2c1-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c2_pins_a: i2c2 { - pins1 { + i2c2_pins_a: i2c2-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c3_pins_a: i2c3 { - pins1 { + i2c3_pins_a: i2c3-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c4_pins_a: i2c4 { - pins1 { + i2c4_pins_a: i2c4-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c6_pins_a: i2c6 { - pins1 { + i2c6_pins_a: i2c6-pins { + pins-bus { pinmux = , ; bias-disable; From 846348a699f9cf9fba4188870b929f88e7556cc1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:39 +0100 Subject: [PATCH 28/47] arm64: dts: mediatek: mt8183-evb: Fix dtbs_check warnings Change the Murata NCM03WF104 node name from "thermal-sensor" to "thermistor" (as that's what it is, after all), and change all of the pinmux main nodes to have a "-pins" suffix to satisfy devicetree bindings checks. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++++++++++----------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index f04baea5d6cb..acfdd5fb041f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -38,7 +38,7 @@ }; }; - thermal-sensor { + thermistor { compatible = "murata,ncp03wf104"; pullup-uv = <1800000>; pullup-ohm = <390000>; @@ -155,7 +155,7 @@ }; &pio { - i2c_pins_0: i2c0 { + i2c_pins_0: i2c0-pins { pins_i2c { pinmux = , ; @@ -163,7 +163,7 @@ }; }; - i2c_pins_1: i2c1 { + i2c_pins_1: i2c1-pins { pins_i2c { pinmux = , ; @@ -171,7 +171,7 @@ }; }; - i2c_pins_2: i2c2 { + i2c_pins_2: i2c2-pins { pins_i2c { pinmux = , ; @@ -179,7 +179,7 @@ }; }; - i2c_pins_3: i2c3 { + i2c_pins_3: i2c3-pins { pins_i2c { pinmux = , ; @@ -187,7 +187,7 @@ }; }; - i2c_pins_4: i2c4 { + i2c_pins_4: i2c4-pins { pins_i2c { pinmux = , ; @@ -195,7 +195,7 @@ }; }; - i2c_pins_5: i2c5 { + i2c_pins_5: i2c5-pins { pins_i2c { pinmux = , ; @@ -203,7 +203,7 @@ }; }; - spi_pins_0: spi0 { + spi_pins_0: spi0-pins { pins_spi { pinmux = , , @@ -213,7 +213,7 @@ }; }; - mmc0_pins_default: mmc0default { + mmc0_pins_default: mmc0-default-pins { pins_cmd_dat { pinmux = , , @@ -239,7 +239,7 @@ }; }; - mmc0_pins_uhs: mmc0 { + mmc0_pins_uhs: mmc0-uhs-pins { pins_cmd_dat { pinmux = , , @@ -274,7 +274,7 @@ }; }; - mmc1_pins_default: mmc1default { + mmc1_pins_default: mmc1-default-pins { pins_cmd_dat { pinmux = , , @@ -298,7 +298,7 @@ }; }; - mmc1_pins_uhs: mmc1 { + mmc1_pins_uhs: mmc1-pins { pins_cmd_dat { pinmux = , , @@ -318,7 +318,7 @@ }; }; - spi_pins_1: spi1 { + spi_pins_1: spi1-pins { pins_spi { pinmux = , , @@ -328,7 +328,7 @@ }; }; - spi_pins_2: spi2 { + spi_pins_2: spi2-pins { pins_spi { pinmux = , , @@ -338,7 +338,7 @@ }; }; - spi_pins_3: spi3 { + spi_pins_3: spi3-pins { pins_spi { pinmux = , , @@ -348,7 +348,7 @@ }; }; - spi_pins_4: spi4 { + spi_pins_4: spi4-pins { pins_spi { pinmux = , , @@ -358,7 +358,7 @@ }; }; - spi_pins_5: spi5 { + spi_pins_5: spi5-pins { pins_spi { pinmux = , , @@ -368,7 +368,7 @@ }; }; - pwm_pins_1: pwm1 { + pwm_pins_1: pwm1-pins { pins_pwm { pinmux = ; }; From 55828e41e7398b630b036eabf3329828706491a0 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:40 +0100 Subject: [PATCH 29/47] arm64: dts: mediatek: mt7981b-openwrt-one: Remove useless cells from flash@0 In spi2's flash@0 there is only one `partitions` subnode: this alone makes specifying address and size cells useless, but then this subnode has no address and no size, which even makes the currently declared address/size cells wrong. Fixes: 869b3bb5ada2 ("arm64: dts: mediatek: mt7981b-openwrt-one: Enable SPI NOR") Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 3de368c73bc8..48b80af90438 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -213,8 +213,6 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; - #address-cells = <1>; - #size-cells = <1>; partitions { compatible = "fixed-partitions"; From b1fc81a986c9b8089db31e21a372cc8b6514e900 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:41 +0100 Subject: [PATCH 30/47] arm64: dts: mediatek: mt8183-jacuzzi-pico6: Fix typo in pinmux node Rename "piins-bt-wakeup" to "pins-bt-wakeup" to fix a dtbs_check warning happening due to this typo. Fixes: 055ef10ccdd4 ("arm64: dts: mt8183: Add jacuzzi pico/pico6 board") Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts index cce326aec1aa..40af5656d6f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -91,7 +91,7 @@ &pio { bt_pins_wakeup: bt-pins-wakeup { - piins-bt-wakeup { + pins-bt-wakeup { pinmux = ; input-enable; }; From 08076645d9ac216b5d78930f52d4fc4d6807cd22 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:42 +0100 Subject: [PATCH 31/47] arm64: dts: mediatek: mt8183-pumpkin: Fix pinmux node names Change all of the pinmux main nodes to have a "-pins" suffix to satisfy devicetree bindings checks. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index f60ef3e53a09..e47955602c83 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -241,7 +241,7 @@ }; &pio { - i2c_pins_0: i2c0 { + i2c_pins_0: i2c0-pins { pins_i2c { pinmux = , ; @@ -249,7 +249,7 @@ }; }; - i2c_pins_1: i2c1 { + i2c_pins_1: i2c1-pins { pins_i2c { pinmux = , ; @@ -257,7 +257,7 @@ }; }; - i2c_pins_2: i2c2 { + i2c_pins_2: i2c2-pins { pins_i2c { pinmux = , ; @@ -265,7 +265,7 @@ }; }; - i2c_pins_3: i2c3 { + i2c_pins_3: i2c3-pins { pins_i2c { pinmux = , ; @@ -273,7 +273,7 @@ }; }; - i2c_pins_4: i2c4 { + i2c_pins_4: i2c4-pins { pins_i2c { pinmux = , ; @@ -281,7 +281,7 @@ }; }; - i2c_pins_5: i2c5 { + i2c_pins_5: i2c5-pins { pins_i2c { pinmux = , ; @@ -289,7 +289,7 @@ }; }; - i2c6_pins: i2c6 { + i2c6_pins: i2c6-pins { pins_cmd_dat { pinmux = , ; @@ -297,7 +297,7 @@ }; }; - keyboard_pins: keyboard { + keyboard_pins: keyboard-pins { pins_keyboard { pinmux = , , From 870ffe2999b5b558e2e6bfc7e7c6324130f08e47 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:43 +0100 Subject: [PATCH 32/47] arm64: dts: mediatek: mt8173-elm: Fix bluetooth node name and reorder Change the node name for Marvell SD8897 SDIO Bluetooth from `btmrvl@2` to `bluetooth@2` to fix a dtbs_check warning. While at it, also change the WiFi one from `mwifiex@1" to a generic "wifi@1" and reorder the nodes so that wifi@1 comes before bluetooth@2. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 9ec930058b92..59813fff7833 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -432,20 +432,20 @@ #address-cells = <1>; #size-cells = <0>; - btmrvl: btmrvl@2 { + mwifiex: wifi@1 { + compatible = "marvell,sd8897"; + reg = <1>; + interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = <3>; + }; + + btmrvl: bluetooth@2 { compatible = "marvell,sd8897-bt"; reg = <2>; interrupts-extended = <&pio 119 IRQ_TYPE_LEVEL_LOW>; marvell,wakeup-pin = /bits/ 16 <0x0d>; marvell,wakeup-gap-ms = /bits/ 16 <0x64>; }; - - mwifiex: mwifiex@1 { - compatible = "marvell,sd8897"; - reg = <1>; - interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = <3>; - }; }; &nor_flash { From 6c0ecd0ae8f64b8d70ba3522ef6903753425e2c4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:44 +0100 Subject: [PATCH 33/47] arm64: dts: mediatek: mt8173-elm: Fix dsi0 ports warning Since only a single port is present, remove the inner `ports` parent node and just declare the single port as `port`. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 59813fff7833..dc064cdcedb5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -206,11 +206,9 @@ &dsi0 { status = "okay"; - ports { - port { - dsi0_out: endpoint { - remote-endpoint = <&ps8640_in>; - }; + port { + dsi0_out: endpoint { + remote-endpoint = <&ps8640_in>; }; }; }; From 04ccbc5325ccd2b96ef5c3dde1a50495980404c8 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:45 +0100 Subject: [PATCH 34/47] arm64: dts: mediatek: mt8173-elm: Remove regulators from thermal node The only reason to have a regulator in the thermal node is to keep the CPU cores up while reading temperatures, but this is incorrect because the AUXADC Thermal IP doesn't need any regulators to work, at all. Since the thermal node was inherited only for adding vregs, remove it entirely. This change is safe also because, among other things, the actual driver never used those regulators anyway. This also fixes a dtbs_check warning. Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index dc064cdcedb5..a0573bc359fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1147,11 +1147,6 @@ status = "okay"; }; -&thermal { - bank0-supply = <&mt6397_vpca15_reg>; - bank1-supply = <&da9211_vcpu_reg>; -}; - &uart0 { status = "okay"; }; From 96cb8d6257d65e74f9c91a382f71a830393467a5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:46 +0100 Subject: [PATCH 35/47] arm64: dts: mediatek: mt8192-asurada: Remove unused clock-stretch-ns Remove the clock-stretch-ns property from i2c2, as it has always been (and still is) unused. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 0b4664f044a1..eadf1b2d156f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -344,7 +344,6 @@ status = "okay"; clock-frequency = <400000>; - clock-stretch-ns = <12600>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; From ab3a124fe08948bb217d1e146f4a8ecd066f63d7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:47 +0100 Subject: [PATCH 36/47] arm64: dts: mediatek: mt6795-xperia-m5: Add UHS pins for MMC1 and 2 Add the UHS state pins for the MMC1 and MMC2 controllers and, while at it, also add the correct drive strength parameters for the default pin states for those two. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt6795-sony-xperia-m5.dts | 48 ++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index fccb948cfa45..ecd13d089ceb 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -227,8 +227,9 @@ &mmc1 { /* MicroSD card slot */ - pinctrl-names = "default"; + pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -236,8 +237,9 @@ &mmc2 { /* SDIO WiFi on MMC2 */ - pinctrl-names = "default"; + pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_uhs>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -324,11 +326,32 @@ ; input-enable; bias-pull-up = ; + drive-strength = <4>; }; pins-clk { pinmux = ; bias-pull-down = ; + drive-strength = <4>; + }; + }; + + mmc1_pins_uhs: microsd-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + drive-strength = <6>; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + drive-strength = <8>; }; }; @@ -341,11 +364,32 @@ ; input-enable; bias-pull-up = ; + drive-strength = <4>; }; pins-clk { pinmux = ; bias-pull-down = ; + drive-strength = <4>; + }; + }; + + mmc2_pins_uhs: sdio-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + drive-strength = <8>; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + drive-strength = <8>; }; }; From 178c08fd8ce53c77910fb16cc99e932049b6c6e8 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 13 Jan 2026 11:59:58 +0100 Subject: [PATCH 37/47] arm64: dts: mediatek: mt6331: Fix VCAM IO regulator name The ldo-vcamio regulator is named "vcam_io", however, the binding only allows "vcamio" as name: change it to the latter to resolve a dtbs_check warning. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6331.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi index 243afbffa21f..7e7b96e8ca6f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6331.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi @@ -217,7 +217,7 @@ }; mt6331_vcamio_reg: ldo-vcamio { - regulator-name = "vcam_io"; + regulator-name = "vcamio"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1800000>; regulator-ramp-delay = <0>; From aec5445dd7c8c6c84d46f2dbf07967ac54393595 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 13 Jan 2026 11:59:59 +0100 Subject: [PATCH 38/47] arm64: dts: mediatek: mt6795: Fix issues in SCPSYS node Add the "mediatek,mt6795-scpsys" compatible to the SCPSYS node and remove #power-domain-cells (retaining it only in the power controller subnode) to resolve dtbs_check warnings. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 58833e5135c8..ae2aaa51c9ad 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -287,9 +287,8 @@ }; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt6795-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { From a40901fe6f5c27856b7112a6e635b13446ec4c7b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 13 Jan 2026 12:00:00 +0100 Subject: [PATCH 39/47] arm64: dts: mediatek: mt6795-xperia-m5: Rename PMIC leds node The MT6332 PMIC leds node was named "mt6332-led", however, the binding rightfully enforces using the generic node name "leds". Change it to the latter to resolve dtbs_check warnings. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index ecd13d089ceb..0e086dd487d9 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -507,7 +507,7 @@ */ interrupts = ; - mt6332-led { + leds { compatible = "mediatek,mt6332-led"; #address-cells = <1>; #size-cells = <0>; From 093d6e332259583a94d630897bdb07d6141bff57 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 13 Jan 2026 12:00:26 +0100 Subject: [PATCH 40/47] arm64: dts: mediatek: mt8173-evb: Add interrupts to DA9211 regulator Add the required pinmux and assign the right interrupts-extended to the DA9211 regulator (PIO pin 15). Reviewed-by: Matthias Brugger Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 51118a4149d8..1049877e6cda 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -117,6 +117,7 @@ buck: da9211@68 { compatible = "dlg,da9211"; reg = <0x68>; + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; regulators { da9211_vcpu_reg: BUCKA { @@ -179,6 +180,13 @@ }; }; + i2c1_pins_a: i2c1-pins { + pins-da9211 { + pinmux = ; + bias-pull-up; + }; + }; + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = , From 32c5491a8d73713578560f515cccd4e9460d156d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 12 Jan 2026 15:55:58 +0100 Subject: [PATCH 41/47] arm64: dts: mediatek: mt7986a: Change compatible for SafeXcel crypto Following the changes in the binding for the SafeXcel crypto engine, add a SoC specific compatible to the existing crypto node and, while at it, also change the fallback compatible to inside-secure,safexcel-eip97ies as the eip97 one is deprecated. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 7790601586cc..9693f62fd013 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -231,7 +231,7 @@ }; crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; + compatible = "mediatek,mt7986-crypto", "inside-secure,safexcel-eip97ies"; reg = <0 0x10320000 0 0x40000>; interrupts = , , From d33d77044c37aa97f24e3e3adf2f781aba774db2 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 14 Jan 2026 17:26:04 +0800 Subject: [PATCH 42/47] arm64: dts: mediatek: mt8183-kukui: Clean up IT6505 regulator supply Align the name of the regulator with the design schematic. Also fix up the gpio property to the new "gpios" property name, and add the GPIO_ACTIVE_HIGH flag. The flag is actively ignored in Linux in favor of the old "enable-active-high" property; nevertheless it is the correct description. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 4b87d4940c8c..a8e257b21a88 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -44,10 +44,10 @@ clock-output-names = "clk32k"; }; - it6505_pp18_reg: regulator0 { + pp1800_it6505: regulator0 { compatible = "regulator-fixed"; - regulator-name = "it6505_pp18"; - gpio = <&pio 178 0>; + regulator-name = "pp1800_it6505"; + gpios = <&pio 178 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&pp1800_alw>; }; From e9858fba558ced73133a685c8e76c04cb66d8244 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 11:41:12 +0100 Subject: [PATCH 43/47] arm64: dts: mediatek: mt7981b-openwrt-one: Add address/size cells to eth The ethernet node has two MAC subnodes and cannot use the default address/size cells: set address cells to 1 and size cells to 0. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 48b80af90438..b7ff7b8e1375 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -90,6 +90,8 @@ }; ð { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; /* WAN interface */ From 615962473ba6ecde7da61d89adf85062972c2c4c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 12:36:08 +0100 Subject: [PATCH 44/47] arm64: dts: mediatek: mt8186-evb: Add vproc fixed regulator This board at the moment has no support for PMIC regulators, but the CCI requires a vproc regulator in order to both stop giving dtbs_check warnings and to actually probe. Since vproc is a system-critical regulator and the bootloader enables it at max voltage, model it (at least temporarily) as a regulator-fixed and assign it to CCI. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts index 2667a7424200..a941a931a07c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -22,6 +22,19 @@ device_type = "memory"; reg = <0 0x40000000 0 0x80000000>; }; + + vproc: regulator-vproc12 { + compatible = "regulator-fixed"; + regulator-name = "vproc12"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; +}; + +&cci { + proc-supply = <&vproc>; }; &i2c0 { From e1c9223adf1c2b7d84f29f2e7e6d9a4f749da2c0 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 14:10:35 +0100 Subject: [PATCH 45/47] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address The PCIe and USB TPHYs are under the soc bus, which provides MMIO, and all nodes under that must use the bus, otherwise those would clearly be out of place. Add ranges to both the tphy(s) and assign the address to the main node to silence a dtbs_check warning, and fix the children to use the MMIO range of t-phy. Fixes: ("f693e6ba55ae arm64: dts: mediatek: mt7988: Add t-phy for ssusb1") Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 28 +++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index bec590d26659..8c9a5aba2579 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -629,20 +629,20 @@ tphy: t-phy@11c50000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x1000>; status = "disabled"; - tphyu2port0: usb-phy@11c50000 { - reg = <0 0x11c50000 0 0x700>; + tphyu2port0: usb-phy@0 { + reg = <0 0x700>; clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; clock-names = "ref"; #phy-cells = <1>; }; - tphyu3port0: usb-phy@11c50700 { - reg = <0 0x11c50700 0 0x900>; + tphyu3port0: usb-phy@700 { + reg = <0x700 0x900>; clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; clock-names = "ref"; #phy-cells = <1>; @@ -659,20 +659,20 @@ xsphy: xs-phy@11e10000 { compatible = "mediatek,mt7988-xsphy", "mediatek,xsphy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e10000 0x3900>; status = "disabled"; - xphyu2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x400>; + xphyu2port0: usb-phy@0 { + reg = <0 0x400>; clocks = <&infracfg CLK_INFRA_USB_UTMI>; clock-names = "ref"; #phy-cells = <1>; }; - xphyu3port0: usb-phy@11e13000 { - reg = <0 0x11e13400 0 0x500>; + xphyu3port0: usb-phy@3400 { + reg = <0x3400 0x500>; clocks = <&infracfg CLK_INFRA_USB_PIPE>; clock-names = "ref"; #phy-cells = <1>; From a8e3d66ff5c0c37e7c10b3e486d2c5047bf9cf2b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 13:56:23 +0100 Subject: [PATCH 46/47] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant Add support for the mediatek,mt8192-audsys compatible, which uses a different audio controller (mt8192-afe-pcm) compared to mt8183 and mt2701. This resolves a dtbs_check warning on all MT8192 devicetrees. Reviewed-by: Rob Herring (Arm) Signed-off-by: AngeloGioacchino Del Regno --- .../arm/mediatek/mediatek,audsys.yaml | 46 +++++++++++++------ 1 file changed, 33 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml index f3a761cbd0fd..09a6c16e7e82 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -48,19 +48,39 @@ required: - compatible - '#clock-cells' -if: - properties: - compatible: - contains: - const: mediatek,mt8183-audiosys -then: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt8183-audio.yaml# -else: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt2701-audio.yaml# +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-audsys + - mediatek,mt7622-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-audiosys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt8183-audio.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mt8192-afe-pcm.yaml# + additionalProperties: false From 25556c12f4d3edc2f614f752f204c3941697b30a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 13:56:24 +0100 Subject: [PATCH 47/47] arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to audio-controller Device tree nodes should have generic names, and this one doesn't. Rename the mt8192-afe-pcm subnode of audsys to `audio-controller`. This commit brings no functional changes, but resolves dtbs_check warnings. Acked-by: Rob Herring (Arm) Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 47dea10dd3b8..9f8f115edd4c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -973,7 +973,7 @@ reg = <0 0x11210000 0 0x2000>; #clock-cells = <1>; - afe: mt8192-afe-pcm { + afe: audio-controller { compatible = "mediatek,mt8192-audio"; interrupts = ; resets = <&watchdog 17>;