microblaze: Clear all MSR flags on the first kernel instruction

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The main reason is bug because of dynamic TLB allocation.
U-BOOT didn't disable dcache and then writing to physical address
from ASM wan't visible for reading through MMU.
Disabling caches and clearing all flags from previous code
is good to do so.

Signed-off-by: Michal Simek <monstr@monstr.eu>

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This commit is contained in:

Michal Simek 2011-11-09 15:39:58 +01:00

parent cc5647a64e

commit 173701d774

1 changed files with 2 additions and 3 deletions

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arch/microblaze/kernel/head.S

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