perf: riscv: preliminary RISC-V support

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This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles.  Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.

riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-Spec.  Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes.  Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.

Cc: Nick Hu <nickhu@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Signed-off-by: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

...

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Alan Kao 2018-04-20 07:27:49 +08:00 • committed by Palmer Dabbelt

parent 29dcea8877

commit 178e9fc47a

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14

arch/riscv/Kconfig

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1

arch/riscv/include/asm/Kbuild

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84

arch/riscv/include/asm/perf_event.h

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2

arch/riscv/kernel/Makefile

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485

arch/riscv/kernel/perf_event.c

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