i.MX clock drivers update for 5.7:

- A series from Anson to convert i.MX8 clock bindings to json-schema. - Update pll14xx driver to include new frequency entries for pll1443x table, and return error for invalid PLL type. - Clean up header includes and unnecessary code on a few clock driver. - Add mssing of_node_put() call for a number of clock drivers. - Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already have the flag on its child cpu clock. - Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL via CORE_SEL slice, and source from A53 CCM clk root when we need to change ARM PLL frequency. Thus, we can support core running above 1GHz safely. - Update pfdv2 driver to check zero rate and use determine_rate for getting the best rate. - Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl5vHoUUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM6lNgf/Qe1jojmzjLPD/QhC31sDrQMTZ+vQ K309EiXjcZdJ8QTIRTO9IIPHYzy82vjCNywzdy1azQEmPAqDj+MPAjRLu3KLFjr5 husU0wzSdGvkPQ7d4w+GI/4KfeP0evyXFioGyMKF//iFUKrurSc08ZbMBNtLsrQu a6iTia2+1UDzKbN5grKNu/JKYdAceoca1fRNCvkoysKUnqOm9be5eT0QfA7v+V8A I8qhGjKAzI8R2cfxuxRAG9Zw3/b2nbvzngkRMauId7nkD+gYTcP4q9la1ZibbR68 K6lZqjpi5BTN+5cDxkI3ezEstGshVJvd5jDeh2IIzcFCdeG5JF/pUsbZ+A== =h3BT -----END PGP SIGNATURE----- Merge tag 'clk-imx-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX clk driver updates from Shawn Guo: - A series from Anson to convert i.MX8 clock bindings to json-schema - Update pll14xx driver to include new frequency entries for pll1443x table, and return error for invalid PLL type - Clean up header includes and unnecessary code on a few clock driver - Add mssing of_node_put() call for a number of clock drivers - Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already have the flag on its child cpu clock - Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL via CORE_SEL slice, and source from A53 CCM clk root when we need to change ARM PLL frequency. Thus, we can support core running above 1GHz safely - Update pfdv2 driver to check zero rate and use determine_rate for getting the best rate - Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d * tag 'clk-imx-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits) clk: imx: clk-gate2: Pass the device to the register function clk: imx7d: Add PXP clock clk: imx8mq: A53 core clock no need to be critical clk: imx8mp: A53 core clock no need to be critical clk: imx8mm: A53 core clock no need to be critical clk: imx8mn: A53 core clock no need to be critical clk: imx: pllv4: use prepare/unprepare clk: imx: pfdv2: determine best parent rate clk: imx: pfdv2: switch to use determine_rate clk: imx: Fix division by zero warning on pfdv2 clk: imx: clk-sscg-pll: Drop unnecessary initialization clk: imx: pll14xx: Return error if pll type is invalid clk: imx: imx8mp: fix a53 cpu clock clk: imx: imx8mn: fix a53 cpu clock clk: imx: imx8mm: fix a53 cpu clock clk: imx: imx8mq: fix a53 cpu clock clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock clk: imx8mn: Remove unused includes clk: imx8mm: Remove unused includes clk: imx8mp: Include slab.h instead of clkdev.h ...
2026-10-16 22:39:48 +00:00 · 2020-03-24 19:23:49 -07:00 · 2020-03-24 19:23:49 -07:00 · 17bbcd7d5f
commit 17bbcd7d5f
parent bb6d3fb354 b5881e8019
26 changed files with 383 additions and 211 deletions
--- a/Documentation/devicetree/bindings/clock/imx8mm-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx8mm-clock.txt
--- a/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml
--- a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
--- a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt
--- a/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
--- a/drivers/clk/imx/clk-fixup-div.c
+++ b/drivers/clk/imx/clk-fixup-div.c
--- a/drivers/clk/imx/clk-fixup-mux.c
+++ b/drivers/clk/imx/clk-fixup-mux.c
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
--- a/drivers/clk/imx/clk-pfdv2.c
+++ b/drivers/clk/imx/clk-pfdv2.c
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
--- a/drivers/clk/imx/clk-pllv4.c
+++ b/drivers/clk/imx/clk-pllv4.c
--- a/drivers/clk/imx/clk-sscg-pll.c
+++ b/drivers/clk/imx/clk-sscg-pll.c
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h