net/mlx5: DR, Fix QP continuous allocation

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When allocating a QP we allocate an RQ and an SQ, the RQ is stored first
in memory and followed by the SQ.
This allocation is not physically continiuos - it may span across different
physical pages. SW Steering code always writes in pairs: 1BB write + 1BB read,
or 2 continuous BBs of GTA WQE.

This lead to an issue where RQ allocation was 4x16 which is equal to 1 WQE BB,
causing 1 BB offset in the page and splitting the GTA WQE between different
physical pages.

The solution was to create the RQ with a even number of BBs and to have the
RQ aligned to a page.

Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

...

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Yevgeny Kliteynik 2022-11-15 00:11:38 +02:00 • committed by Saeed Mahameed

parent 7d7c9453d6

commit 17dc71c336

1 changed files with 1 additions and 1 deletions

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drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c

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