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- pll fixes for GXBB, GXL and AXG
- use regmap in clock controllers for GXBB, GXL and AXG - general clock updates for Meson8, GXBB, GXL and AXG Based on the clk-helpers topic branch as a dependency. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJap5YzAAoJEHfc29rIyEnRtxgQAJ+KgOifsPex8pjqSm50akLx 4eQJA1xteu5TEipC66eSM0/EyHyVHhShaqYQcNZmNA0ckI7wZkii4+EXPvrCxlyR ZvEs98BpPZKsZQ58yrKQ44AHdFREDnMF+9vDzklRhKzp676s9o9+IxowfAxCIWlz e4mpMOTwqRYMPVN1WabHCjVsmwkMR0d1+1JpoV1uZHJXYBBc2Rrd0BhoL9Ma9uiC Rr9osS97O8/xsk1bn6o1CLHhvLylvDw9rY6jSh2FltM7S6kkgg4SDdIvXc3unx2i ZpxQP9+f/TslAvXRh5ejOq7xPvOtXXqvCDbU5Vs226n3rwpTEhHrjSFCsmPB+C/d 1+B2bEELTapDHiq0s3JY3GP9Ks58RWwJzsaOwvh/3TVr2hvsJeQaiVUDqsyJ7nLu QEaaIhGtImw1WFyxghoc6IU9JH7Y/w41GioGg8rQEAhs+iKI6RQ9ZnO5TFW7aelQ VUYnWWCY/amJYoPdoMqNZVsDXqCJO7JmhB79t2Ssp9pOkipSHspzTemuT/+aqhU4 GGS3iKl2SE42KYbu5EK+YdVynWPd72swtRAu985D7K+4UToyhbRSXFm6XBubt1fw 99BdC5yGcyr1ShPmHAjTlL8+GttN74c4af7mvZgPom15g6bZw22e3X2LRmT1mL7z OQbsseAj9SZzxMtm83rK =TpHi -----END PGP SIGNATURE----- Merge tag 'clk-for-v4.17-1' of https://github.com/BayLibre/clk-meson into clk-amlogic Pull amlogic clk driver updates from Neil Armstrong: - pll fixes for GXBB, GXL and AXG - use regmap in clock controllers for GXBB, GXL and AXG - general clock updates for Meson8, GXBB, GXL and AXG (Based on the clk-helpers topic branch as a dependency) * tag 'clk-for-v4.17-1' of https://github.com/BayLibre/clk-meson: (49 commits) clk: meson: clean-up clk81 clocks clk: meson: add fdiv clock gates clk: meson: add mpll pre-divider clk: meson: axg: add hifi pll clock clk: meson: axg: add hifi clock bindings clk: meson: add ROUND_CLOSEST to the pll driver clk: meson: add gp0 frac parameter for axg and gxl clk: meson: improve pll driver results with frac clk: meson: remove special gp0 lock loop clk: meson: poke pll CNTL last clk: meson: add fractional part of meson8b fixed_pll clk: meson: use hhi syscon if available clk: meson: remove obsolete cpu_clk clk: meson: rework meson8b cpu clock clk: meson: split divider and gate part of mpll clk: meson: migrate plls clocks to clk_regmap clk: meson: migrate the audio divider clock to clk_regmap clk: meson: migrate mplls clocks to clk_regmap clk: meson: add regmap helpers for parm clk: meson: migrate muxes to clk_regmap ...
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