drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

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RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Rohit Khaire 2021-06-04 11:02:56 -04:00 • committed by Alex Deucher

parent 810085ddb7

commit 18703923a6

1 changed files with 21 additions and 5 deletions

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26

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

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