drm/radeon: rework crtc pll setup to better support PPLL sharing

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We need the calculate the pixel clock before allocating a PPLL
in order to insure the clocks really match.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Alex Deucher 2012-09-13 10:56:16 -04:00

parent 2f454cf126

commit 19eca43e5a

2 changed files with 150 additions and 103 deletions

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277

drivers/gpu/drm/radeon/atombios_crtc.c

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32

drivers/gpu/drm/radeon/radeon_mode.h

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