From 42e4d6d5d495447d1c98b1ea8eec38017878c840 Mon Sep 17 00:00:00 2001 From: James Liao Date: Wed, 28 Dec 2016 13:46:44 +0800 Subject: [PATCH 1/9] arm: dts: mt2701: Sort DT nodes by register address This patch rearrange MT2701 DT nodes to keep them in ascending order. Signed-off-by: James Liao [mb: fix pio unit address and order] Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 7eab6f4c4665..f3824e7dfa5a 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -96,24 +96,6 @@ timer { ; }; - pio: pinctrl@10005000 { - compatible = "mediatek,mt2701-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - ; - }; - - syscfg_pctl_a: syscfg@10005000 { - compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - topckgen: syscon@10000000 { compatible = "mediatek,mt2701-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; @@ -134,6 +116,11 @@ pericfg: syscon@10003000 { #reset-cells = <1>; }; + syscfg_pctl_a: syscfg@10005000 { + compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt2701-wdt", "mediatek,mt6589-wdt"; @@ -149,6 +136,19 @@ timer: timer@10008000 { clock-names = "system-clk", "rtc-clk"; }; + pio: pinctrl@1000b000 { + compatible = "mediatek,mt2701-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + }; + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq"; From f235c7e7a75325f28a33559a71f25a0eca6112db Mon Sep 17 00:00:00 2001 From: James Liao Date: Wed, 28 Dec 2016 13:46:45 +0800 Subject: [PATCH 2/9] arm: dts: mt2701: Add subsystem clock controller device nodes Add MT2701 subsystem clock controllers, inlcude mmsys, imgsys, vdecsys, hifsys, ethsys and bdpsys. Signed-off-by: James Liao Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 36 +++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index f3824e7dfa5a..8623c3e7a474 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -214,4 +214,40 @@ uart3: serial@11005000 { clock-names = "baud", "bus"; status = "disabled"; }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt2701-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt2701-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt2701-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt2701-hifsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt2701-ethsys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + bdpsys: syscon@1c000000 { + compatible = "mediatek,mt2701-bdpsys", "syscon"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; + }; }; From 9f3746aff970b0155380dc892db7054736fb6554 Mon Sep 17 00:00:00 2001 From: James Liao Date: Wed, 28 Dec 2016 13:46:46 +0800 Subject: [PATCH 3/9] arm: dts: mt2701: Add power domain controller device node Add power domain controller node (scpsys) for MT2701. Signed-off-by: James Liao Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 8623c3e7a474..32ab356fea5b 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -121,6 +122,17 @@ syscfg_pctl_a: syscfg@10005000 { reg = <0 0x10005000 0 0x1000>; }; + scpsys: scpsys@10006000 { + compatible = "mediatek,mt2701-scpsys", "syscon"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + infracfg = <&infracfg>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_ETHIF_SEL>; + clock-names = "mm", "mfg", "ethif"; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt2701-wdt", "mediatek,mt6589-wdt"; From 571b95894d70bbdfa032fd31e99e130c86c2a783 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Tue, 20 Dec 2016 20:04:34 +0100 Subject: [PATCH 4/9] ARM: dts: mediatek: update my email address This patch updates my email address as I no longer have access to the old one. Signed-off-by: John Crispin Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623-evb.dts | 2 +- arch/arm/boot/dts/mt7623.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts index a9ee2d64c6f7..b60b41cad592 100644 --- a/arch/arm/boot/dts/mt7623-evb.dts +++ b/arch/arm/boot/dts/mt7623-evb.dts @@ -1,6 +1,6 @@ /* * Copyright (c) 2016 MediaTek Inc. - * Author: John Crispin + * Author: John Crispin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index fd2b614ae6f3..6af8e6041bb7 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -1,6 +1,6 @@ /* * Copyright (c) 2016 MediaTek Inc. - * Author: John Crispin + * Author: John Crispin * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as From f3cba0f49c7ce4955741793f6b96e1e237eb2ba2 Mon Sep 17 00:00:00 2001 From: Honghui Zhang Date: Wed, 8 Jun 2016 17:51:01 +0800 Subject: [PATCH 5/9] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701 Add the dtsi node of iommu and smi for mt2701. Signed-off-by: Honghui Zhang Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 50 +++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 32ab356fea5b..ae3c7d0f2d14 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -161,6 +161,16 @@ pio: pinctrl@1000b000 { ; }; + smi_common: smi@1000c000 { + compatible = "mediatek,mt2701-smi-common"; + reg = <0 0x1000c000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_SMI>, + <&mmsys CLK_MM_SMI_COMMON>, + <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi", "async"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq"; @@ -170,6 +180,16 @@ sysirq: interrupt-controller@10200100 { reg = <0 0x10200100 0 0x1c>; }; + iommu: mmsys_iommu@10205000 { + compatible = "mediatek,mt2701-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2>; + #iommu-cells = <1>; + }; + apmixedsys: syscon@10209000 { compatible = "mediatek,mt2701-apmixedsys", "syscon"; reg = <0 0x10209000 0 0x1000>; @@ -233,18 +253,48 @@ mmsys: syscon@14000000 { #clock-cells = <1>; }; + larb0: larb@14010000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x14010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt2701-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + larb2: larb@15001000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_SMI_COMM>, + <&imgsys CLK_IMG_SMI_COMM>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + }; + vdecsys: syscon@16000000 { compatible = "mediatek,mt2701-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb1: larb@16010000 { + compatible = "mediatek,mt2701-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_CKGEN>, + <&vdecsys CLK_VDEC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; + }; + hifsys: syscon@1a000000 { compatible = "mediatek,mt2701-hifsys", "syscon"; reg = <0 0x1a000000 0 0x1000>; From 159f5ae739c89c50881740900724cc8a91a8ef2c Mon Sep 17 00:00:00 2001 From: Leilk Liu Date: Fri, 13 Jan 2017 16:42:53 +0800 Subject: [PATCH 6/9] arm: dts: mt2701: Add spi device node Add spi device node for MT2701. Signed-off-by: Leilk Liu Signed-off-by: Erin Lo Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701-evb.dts | 50 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/mt2701.dtsi | 39 +++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index 082ca8807c62..879f1ebfc16d 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -24,6 +24,56 @@ memory { }; }; +&pio { + spi_pins_a: spi0@0 { + pins_spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi_pins_b: spi1@0 { + pins_spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi_pins_c: spi2@0 { + pins_spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_a>; + status = "disabled"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_b>; + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_c>; + status = "disabled"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index ae3c7d0f2d14..2bfd8afc1c00 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -247,6 +247,45 @@ uart3: serial@11005000 { status = "disabled"; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI0_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11016000 { + compatible = "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11016000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI1_SEL>, + <&pericfg CLK_PERI_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11017000 { + compatible = "mediatek,mt2701-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11017000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI2_SEL>, + <&pericfg CLK_PERI_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt2701-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; From 111758b738cc9190521f75d65cb7987b230fede4 Mon Sep 17 00:00:00 2001 From: Xiaolei Li Date: Fri, 13 Jan 2017 16:42:55 +0800 Subject: [PATCH 7/9] arm: dts: mt2701: Add nand device node Add mt2701 nand device node, include nfi and bch ecc. Signed-off-by: Xiaolei Li Signed-off-by: Erin Lo Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 2bfd8afc1c00..9edf000cf7af 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -260,6 +260,28 @@ spi0: spi@1100a000 { status = "disabled"; }; + nandc: nfi@1100d000 { + compatible = "mediatek,mt2701-nfc"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names = "nfi_clk", "pad_clk"; + status = "disabled"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + }; + + bch: ecc@1100e000 { + compatible = "mediatek,mt2701-ecc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_ECC>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + spi1: spi@11016000 { compatible = "mediatek,mt2701-spi"; #address-cells = <1>; From 301501d3b5eb3e86be01f2584321c9c8f4b9b98b Mon Sep 17 00:00:00 2001 From: Zhiyong Tao Date: Fri, 13 Jan 2017 16:42:56 +0800 Subject: [PATCH 8/9] arm: dts: mt2701: Add auxadc device node. Add auxadc device node for MT2701. Signed-off-by: Zhiyong Tao Signed-off-by: Erin Lo Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701-evb.dts | 4 ++++ arch/arm/boot/dts/mt2701.dtsi | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index 879f1ebfc16d..a4837985b7a7 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -24,6 +24,10 @@ memory { }; }; +&auxadc { + status = "okay"; +}; + &pio { spi_pins_a: spi0@0 { pins_spi { diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 9edf000cf7af..af5c737a10a5 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -207,6 +207,15 @@ gic: interrupt-controller@10211000 { <0 0x10216000 0 0x2000>; }; + auxadc: adc@11001000 { + compatible = "mediatek,mt2701-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt2701-uart", "mediatek,mt6577-uart"; From e348dc74f798c2df31c685bf0c814396f4f3b735 Mon Sep 17 00:00:00 2001 From: Dawei Chien Date: Tue, 17 Jan 2017 17:24:09 +0800 Subject: [PATCH 9/9] arm: dts: mt2701: Add thermal device node. Add thermal controller device nodes for MT2701. Signed-off-by: Dawei Chien Signed-off-by: Erin Lo Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index af5c737a10a5..c88ebd532336 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -88,6 +88,36 @@ rtc32k: oscillator@1 { clock-output-names = "rtc32k"; }; + thermal-zones { + cpu_thermal: cpu_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&thermal 0>; + sustainable-power = <1000>; + + trips { + threshold: trip-point@0 { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point@1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit@0 { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; @@ -269,6 +299,19 @@ spi0: spi@1100a000 { status = "disabled"; }; + thermal: thermal@1100b000 { + #thermal-sensor-cells = <0>; + compatible = "mediatek,mt2701-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT2701_PERI_THERM_SW_RST>; + reset-names = "therm"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + nandc: nfi@1100d000 { compatible = "mediatek,mt2701-nfc"; reg = <0 0x1100d000 0 0x1000>;