i915/display/dp: SDP CRC16 for 128b132b link layer

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Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.

v2: Moved the CRC enable to link training init(Jani N)
v3: Moved crc enable to ddi pre enable <Jani N>
v4: Separate function for SDP CRC16 (Jani N)

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230302081532.765821-3-arun.r.murthy@intel.com

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Arun R Murthy 2023-03-02 13:45:32 +05:30 • committed by Jani Nikula

parent 562334d22a

commit 1a324a40b4

3 changed files with 26 additions and 0 deletions

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4

drivers/gpu/drm/i915/display/intel_ddi.c

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20

drivers/gpu/drm/i915/display/intel_dp_link_training.c

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2

drivers/gpu/drm/i915/display/intel_dp_link_training.h

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