clk: tegra: fix SS control on PLL enable/disable

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PLL SS was only controlled when setting the PLL rate, not when the PLL itself
is enabled or disabled.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Peter De Schrijver 2017-07-25 13:34:02 +03:00 • committed by Stephen Boyd

parent de2245540e

commit 1a7da87727

1 changed files with 24 additions and 20 deletions

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drivers/clk/tegra/clk-pll.c

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