drm/i915/cx0: Enable dpll framework for MTL+

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MTL+ platforms are supported by dpll framework remove a separate
check for hw comparison and rely solely on dpll framework
hw comparison.

Finally, all required hooks are now in place so initialize
PLL manager for MTL+ platforms and remove the redirections
to the legacy code paths from the following interfaces:

* intel_encoder::clock_enable/disable()
* intel_encoder::get_config()
* intel_dpll_funcs::get_hw_state()
* intel_ddi_update_active_dpll()
* pipe_config_pll_mismatch()

v2: Rebase on !HAS_LT_PHY check in intel_ddi_update_active_dpll()
v3: Rebase on !display->dpll.mgr check in intel_ddi_update_active_dpll()
    Add check for NVL as the platform is not part of pll framework (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251118132859.2584452-1-mika.kahola@intel.com

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This commit is contained in:

Mika Kahola 2025-11-18 15:28:59 +02:00

parent 2a6e417907

commit 1a7fad2aea

5 changed files with 6 additions and 86 deletions

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10

drivers/gpu/drm/i915/display/intel_cx0_phy.c

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23

drivers/gpu/drm/i915/display/intel_ddi.c

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29

drivers/gpu/drm/i915/display/intel_display.c

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23

drivers/gpu/drm/i915/display/intel_dpll.c

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7

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

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