spi: cadence-quadspi: allow operations with cmd/addr buswidth >1

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With the removal of the incorrect logic of cqspi_set_protocol(), ops with
cmd/addr buswidth >1 are now working correctly.

Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4
operations.

DTR operations are currently untested, so we leave them disabled for now
(except for the previously allowed 8-8-8 ops).

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20220420155616.281730-2-matthias.schiffer@ew.tq-group.com
Signed-off-by: Mark Brown <broonie@kernel.org>

...

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Matthias Schiffer 2022-04-20 17:56:16 +02:00 • committed by Mark Brown

parent 28ac902aed

commit 1aeda09666

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drivers/spi/spi-cadence-quadspi.c

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