drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros

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Although on HSW/BDW there is only a single display global power well,
it's programmed the same way as other GEN9+ power wells. This also
means we can get at the HSW/BDW request and status flags the same way
it's done on GEN9+ by assigning the corresponding HSW/BDW power well ID.
This ID was assigned in a recent patch, so we can now switch to using
the same macros everywhere on HSW+.

Updating the HSW power well control register with RMW is not strictly
necessary, but this will allow us to use the same code for GEN9+.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1499352040-8819-13-git-send-email-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Imre Deak 2017-07-06 17:40:34 +03:00 • committed by Daniel Vetter

parent ec46d48360

commit 1af474fef2

3 changed files with 44 additions and 30 deletions

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8

drivers/gpu/drm/i915/gvt/handlers.c

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8

drivers/gpu/drm/i915/i915_reg.h

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58

drivers/gpu/drm/i915/intel_runtime_pm.c

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