PCI: sophgo: Disable L0s and L1 on Sophgo 2044 PCIe Root Ports

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[ Upstream commit 613f3255a3 ]

Sophgo 2044 Root Ports advertise L0 and L1 capabilities without supporting
them. Since commit f3ac2ff148 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enabled ASPM on all device tree
platforms, the issue became evident and the SG2044 Root Port started
breaking.

Hence, disable the L0s and L1 capabilities in the LINKCAP register for the
SG2044 Root Ports, so that these states won't get enabled.

Fixes: 467d9c0348 ("PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
[mani: reworded description and corrected fixes tag]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Link: https://patch.msgid.link/20260109040756.731169-1-inochiama@gmail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Inochi Amaoto 2026-01-09 12:07:53 +08:00 • committed by Greg Kroah-Hartman

parent ef42c53b7a

commit 1af7637857

1 changed files with 18 additions and 0 deletions

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drivers/pci/controller/dwc/pcie-sophgo.c

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