clk: renesas: r9a07g044: Add clock and reset entries for ADC

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Add clock and reset entries for ADC block in CPG driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719085840.21842-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2021-07-19 09:58:39 +01:00 • committed by Geert Uytterhoeven

parent 3b5c734592

commit 1b87d5bba3

1 changed files with 6 additions and 0 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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