clk: rs9: Fix DIF OEn bit placement on 9FGV0241

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[ Upstream commit 29d861b5d2 ]

On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other
chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment
the index in BIT() macro instead of the result of BIT() macro to shift
the bit correctly on 9FGV0241.

Fixes: 603df193ec ("clk: rs9: Support device specific dif bit calculation")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://lore.kernel.org/r/20231105200642.62792-1-marek.vasut+renesas@mailbox.org
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Marek Vasut 2023-11-05 21:06:15 +01:00 • committed by Greg Kroah-Hartman

parent 9ca5edf11e

commit 1bbcb2ebc8

1 changed files with 1 additions and 1 deletions

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drivers/clk/clk-renesas-pcie.c

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