drm/amd/display: Extend w/a for hard hang on HPD to dcn20

Browse source

[Why]
HPD disable and enable sequences are not mutually exclusive on Linux.
For HPDs that spans under 1s (i.e. HPD low = 1s), part of the disable
sequence (specifically, a request to SMU to lower refclk) could come
right before the call to PHY enablement, causing DMUB to access an
irresponsive PHY and thus a hard hang on the system.

[How]
Disable 48mhz refclk off when there is any HPD status in connected state
for dcn20.

Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Qingqing Zhuo 2021-08-25 12:29:28 -04:00 • committed by Alex Deucher

parent a62427ef9b

commit 1bd3bc745e

3 changed files with 38 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

12

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

View file

25

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

View file

2

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h

View file