perf, x86: P4 PMU -- update nmi irq statistics and unmask lvt entry properly

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In case if last active performance counter is not overflowed at
moment of NMI being triggered by another counter, the irq
statistics may miss an update stage. As a more serious
consequence -- apic quirk may not be triggered so apic lvt entry
stay masked.

Tested-by: Lin Ming <ming.m.lin@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <20100805150917.GA6311@lenovo>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

...

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Cyrill Gorcunov 2010-08-05 19:09:17 +04:00 • committed by Ingo Molnar

parent ef8f34aabf

commit 1c250d709f

1 changed files with 6 additions and 3 deletions

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arch/x86/kernel/cpu/perf_event_p4.c

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