ASoC: cs42l42: Fix 1536000 Bit Clock instability

Browse source

The 16 Bits, 2 channels, 48K sample rate use case needs
to configure a safer pll_divout during the start of PLL
After 800us from the start of PLL the correct pll_divout
can be set

Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Message-Id: <20210525090822.64577-1-tanureal@opensource.cirrus.com>
Signed-off-by: Mark Brown <broonie@sirena.org.uk>

...

This commit is contained in:

Lucas Tanure 2021-05-25 10:08:19 +01:00 • committed by Mark Brown

parent d4e9889b02

commit 1c52825c38

No known key found for this signature in database

GPG key ID: 24D68B725D5487D0

2 changed files with 33 additions and 16 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

47

sound/soc/codecs/cs42l42.c

View file

2

sound/soc/codecs/cs42l42.h

View file