drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL

Browse source

In case we originally guessed wrong which lcpll vco frequency to use,
we will need to shut down the pll and restart it when reprogamming the
cdclk.

This also allows us to track the actual vco frequency in dev_priv
instead of just a guess.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-8-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

...

This commit is contained in:

Ville Syrjälä 2016-05-13 23:41:26 +03:00

parent 2f2a121aba

commit 1cd593e009

1 changed files with 29 additions and 25 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

54

drivers/gpu/drm/i915/intel_display.c

View file