clk: rockchip: switch PLLs to slow mode before reboot for rk3288

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We've been seeing some crashes at reboot test on rk3288-based systems,
which boards have not reset pin connected to NPOR, they reboot by
setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
a high frequency mode, some IPs might hang during soft reset.
It appears that we can fix the problem by switching to slow mode before
reboot, just like what we did before suspend.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Chris Zhong 2015-11-27 10:09:30 +08:00 • committed by Heiko Stuebner

parent a2f4c560f1

commit 1d33929e2a

1 changed files with 14 additions and 18 deletions

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drivers/clk/rockchip/clk-rk3288.c

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