coresight: etm4x: Cleanup secure exception level masks

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We rely on the ETM architecture version to decide whether
Secure EL2 is available on the CPU for excluding the level
for address comparators and viewinst main control register.
We must instead use the TRCDIDR3.EXLEVEL_S field to detect
the supported levels.

Link: https://lore.kernel.org/r/20210110224850.1880240-16-suzuki.poulose@arm.com
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-18-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Suzuki K Poulose 2021-02-01 11:13:37 -07:00 • committed by Greg Kroah-Hartman

parent 33d5573a15

commit 1d3eead7e9

2 changed files with 7 additions and 12 deletions

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13

drivers/hwtracing/coresight/coresight-etm4x-core.c

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6

drivers/hwtracing/coresight/coresight-etm4x.h

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