drm/i915: Pimp icl+ sagv pre/post update

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Add some debugs on what exactly we're doing to the QGV point mask
in the icl+ sagv pre/post plane update hooks. Currently we're just
guessing.

v2: s/u32/u16/ for consistency with the mask sizes (Stan)

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220218064039.12834-5-ville.syrjala@linux.intel.com

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Ville Syrjälä 2022-02-18 08:40:37 +02:00

parent f257879182

commit 1d82ef6552

1 changed files with 17 additions and 18 deletions

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35

drivers/gpu/drm/i915/intel_pm.c

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