clk: qcom: cmnpll: Add IPQ5332 SoC support

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The CMN PLL in IPQ5332 SoC produces different output clocks when compared
to IPQ9574. While most clock outputs match IPQ9574, the ethernet PHY/switch
(50 Mhz) and PPE clocks (200 Mhz) in IPQ5332 are different.

Add IPQ5332-specific clock definitions and of_device_id entry.

Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-3-f9f7e4efbd79@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

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Luo Jie 2026-01-06 21:35:12 -08:00 • committed by Bjorn Andersson

parent 88c543fff7

commit 1dcbf4195a

1 changed files with 18 additions and 1 deletions

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drivers/clk/qcom/ipq-cmn-pll.c

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