iommu/amd: Check feature support bit before accessing MSI capability registers

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[ Upstream commit 813071438e ]

The IOMMU MMIO access to MSI capability registers is available only if
the EFR[MsiCapMmioSup] is set. Current implementation assumes this bit
is set if the EFR[XtSup] is set, which might not be the case.

Fix by checking the EFR[MsiCapMmioSup] before accessing the MSI address
low/high and MSI data registers via the MMIO.

Fixes: 6692981295 ('iommu/amd: Add support for X2APIC IOMMU interrupts')
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

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Suravee Suthikulpanit 2019-11-20 07:55:48 -06:00 • committed by Greg Kroah-Hartman

parent 08bd511fe9

commit 1f1d48331a

2 changed files with 13 additions and 5 deletions

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17

drivers/iommu/amd_iommu_init.c

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1

drivers/iommu/amd_iommu_types.h

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