clk: meson: mpll: fix mpll0 fractional part ignored

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mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider

Fixes: 007e6e5c5f ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

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Jerome Brunet 2017-07-28 18:32:28 +02:00 • committed by Neil Armstrong

parent 5771a8c088

commit 1f737ffa13

4 changed files with 18 additions and 0 deletions

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7

drivers/clk/meson/clk-mpll.c

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1

drivers/clk/meson/clkc.h

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5

drivers/clk/meson/gxbb.c

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5

drivers/clk/meson/meson8b.c

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