pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets

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SD, PWPR power registers have different offsets b/w RZ/G2L and RZ/G3S.
Add a per SoC configuration data structure that is initialized with the
proper register offsets for individual SoCs.  The rzg2l_hwcfg structure
will be extended further in later commits.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-16-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Claudiu Beznea 2023-09-29 08:39:02 +03:00 • committed by Geert Uytterhoeven

parent 77e18969da

commit 1f89aa906f

1 changed files with 42 additions and 10 deletions

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drivers/pinctrl/renesas/pinctrl-rzg2l.c

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