iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1

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Stage-1 context banks do not have the SMMU_CBn_TCR[SL0] field since it
is only applicable to stage-2 context banks.

This patch ensures that we don't set the reserved TCR bits for stage-1
translations.

Cc: <stable@vger.kernel.org>
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

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Olav Haugan 2014-08-04 19:01:02 +01:00 • committed by Will Deacon

parent a18037b27e

commit 1fc870c7ef

1 changed files with 5 additions and 2 deletions

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drivers/iommu/arm-smmu.c

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