drm/i915: Write to display base last.

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Writing to the DSPBASE register triggers the double-buffered update to
all the control registers, so always write it last in the update
sequence.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>

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Chris Wilson 2010-08-07 11:01:29 +01:00 • committed by Eric Anholt

parent 1d8e1c75ff

commit 20a0945951

1 changed files with 2 additions and 4 deletions

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drivers/gpu/drm/i915/intel_display.c

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