arm64: dts: renesas: r8a779h0: Add L3 cache controller

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Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be

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Duy Nguyen 2024-02-01 15:19:16 +01:00 • committed by Geert Uytterhoeven

parent 93e28f8871

commit 20a942d60b

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