clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor

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Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supported to date.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which has a fixed divisor of 4.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: squashed several patches; rewrote changelog; added r8a774a1 change]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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This commit is contained in:

Takeshi Kihara 2019-03-25 17:35:50 +01:00 • committed by Geert Uytterhoeven

parent 1addd6d568

commit 20cc05ba04

6 changed files with 28 additions and 16 deletions

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4

drivers/clk/renesas/r8a774a1-cpg-mssr.c

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5

drivers/clk/renesas/r8a7795-cpg-mssr.c

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5

drivers/clk/renesas/r8a7796-cpg-mssr.c

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2

drivers/clk/renesas/r8a77965-cpg-mssr.c

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24

drivers/clk/renesas/rcar-gen3-cpg.c

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4

drivers/clk/renesas/rcar-gen3-cpg.h

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