dt-bindings: iommu: Fix interrupt type in example

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The CMDQV interrupt on Tegra264 is edge-triggered per the hardware
interrupt documentation, but the binding example describes it as
level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so
that it does not propagate the wrong trigger type.

Fixes: 8a59954192 ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support")
Reported-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Will Deacon <will@kernel.org>

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Ashish Mhetre 2026-06-22 06:54:09 +00:00 • committed by Will Deacon

parent 7b97226bfb

commit 20df803796

1 changed files with 1 additions and 1 deletions

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Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml

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