clk: renesas: rzv2h: Refactor PLL configuration handling

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Refactor PLL handling by introducing a `struct pll` to encapsulate PLL
configuration parameters, ensuring consistency with the existing dynamic
divider structure.

Introduce the `PLL_PACK()` macro to simplify PLL structure initialization
and update the `DEF_PLL()` macro to use the new `pll` structure. Modify
relevant clock register functions to utilize the structured PLL data
instead of raw configuration values.

This refactoring improves code readability, maintainability, and
alignment with the existing clock configuration approach.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-03-09 21:13:58 +00:00 • committed by Geert Uytterhoeven

parent 0af2f6be1b

commit 20fc4ea6d7

4 changed files with 32 additions and 15 deletions

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2

drivers/clk/renesas/r9a09g047-cpg.c

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2

drivers/clk/renesas/r9a09g057-cpg.c

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drivers/clk/renesas/rzv2h-cpg.c

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drivers/clk/renesas/rzv2h-cpg.h

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