dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs

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Add PLL clock inputs from PLL clock generator.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Xingyu Wu 2023-07-17 10:30:36 +08:00 • committed by Conor Dooley

parent c81f7845b2

commit 2110add84b

1 changed files with 16 additions and 2 deletions

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Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

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