clk: meson: Fix GXL HDMI PLL fractional bits width

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The GXL Documentation specifies 12 bits for the Fractional bit field,
bit the last bits have a different purpose that we cannot handle right
now, so update the bitwidth to have correct fractional calculations.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added comment on GXL HHI_HDMI_PLL_CNTL register shift]
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lkml.kernel.org/r/20181121111922.1277-1-narmstrong@baylibre.com

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Neil Armstrong 2018-11-21 12:19:22 +01:00

parent a7d19b05ce

commit 21310c39ec

1 changed files with 7 additions and 1 deletions

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8

drivers/clk/meson/gxbb.c

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