net/mlx5e: Use the aligned max TX MPWQE size

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TX MPWQE size is limited to the cacheline-aligned maximum. Use the same
value for the stop room and the capability check.

Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

...

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Maxim Mikityanskiy 2022-09-27 13:36:04 -07:00 • committed by Jakub Kicinski

parent e3c4c496dc

commit 21a0502d59

3 changed files with 14 additions and 6 deletions

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8

drivers/net/ethernet/mellanox/mlx5/core/en/params.c

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7

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h

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5

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

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