clk: renesas: r8a77980: Fix RPC-IF module clock's parent

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Testing has shown that the RPC-IF module clock's parent is the RPCD2
clock, not the RPC one -- the RPC-IF register reads stall otherwise...

Fixes: 94e3935b57 ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Sergei Shtylyov 2019-03-07 22:53:19 +03:00 • committed by Geert Uytterhoeven

parent 3c14505c68

commit 21ab095cbc

1 changed files with 1 additions and 1 deletions

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drivers/clk/renesas/r8a77980-cpg-mssr.c

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