cxgb4: Add T5 write combining support

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This patch implements a low latency Write Combining (aka Write Coalescing) work
request path. PCIE maps User Space Doorbell BAR2 region writes to the new
interface to SGE. SGE pulls a new message from PCIE new interface and if its a
coalesced write work request then pushes it for processing. This patch copies
coalesced work request to memory mapped BAR2 space.

Signed-off-by: Santosh Rastapur <santosh@chelsio.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Santosh Rastapur 2013-03-14 05:08:51 +00:00 • committed by David S. Miller

parent 251f9e88a2

commit 22adfe0a85

3 changed files with 102 additions and 5 deletions

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2

drivers/net/ethernet/chelsio/cxgb4/cxgb4.h

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53

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

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52

drivers/net/ethernet/chelsio/cxgb4/sge.c

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