drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state

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The Cx0 PLL enable programming requires the enabled lane count. The PLL
manager framework doesn't pass the CRTC state to the PLL's enable hook,
so prepare here for the conversion to use the PLL manager, by tracking
the enabled lane count in the PLL state as well. This has the advantage,
that the enabled lane count can be verified against the PHY/PLL's
enabled TX lanes.

This also allows dropping the lane count param from the
__intel_cx0pll_enable() function, since it can retrieve this now from
the PLL state.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-9-mika.kahola@intel.com

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Imre Deak 2025-11-17 12:45:38 +02:00 • committed by Mika Kahola

parent 4f8b1e08c2

commit 230d4c7481

2 changed files with 49 additions and 7 deletions

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55

drivers/gpu/drm/i915/display/intel_cx0_phy.c

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1

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

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