powerpc/mm: e300c2/c3/c4 TLB errata workaround

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Complete workaround for DTLB errata in e300c2/c3/c4 processors.

Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.

Based on patch from David Jander <david@protonic.nl>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

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Kumar Gala 2009-03-19 03:55:41 +00:00 • committed by Benjamin Herrenschmidt

parent eb3436a013

commit 2319f12395

4 changed files with 45 additions and 7 deletions

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6

arch/powerpc/include/asm/mmu.h

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5

arch/powerpc/kernel/cpu_setup_6xx.S

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9

arch/powerpc/kernel/cputable.c

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32

arch/powerpc/kernel/head_32.S

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